Supporting Multiple Time Domains In SoC Production Test

An ATPG-to-ATE translation flow for creating high fault-coverage test vectors.


Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for defective wafers and assembled chips is always challenging. Production test engineers constantly struggle to minimize expensive test pattern memory, test each wafer or chip as quickly as possible, and provide a set of test vectors that cover as much of the design functionality as possible.

As in so many other aspects of engineering, tradeoffs must be made. Reducing the number of test vectors saves memory and reduces time but may reduce coverage. Achieving coverage goals may demand a set of test patterns that take too long or require more memory. Taking advantage of advanced ATE features such as repeats and loops may help save memory. Making these tradeoffs properly becomes even more difficult when the SoC being tested has multiple clock domains.

Unfortunately for production test, virtually all modern SoCs do have multiple clocks. At a minimum, most designs have a JTAG Test Access Port (TAP) clock, a scan clock, and a functional clock for normal operation. Many chips also have multiple functional clocks, for example for processors, memories, and standard bus interfaces. The frequencies of these clocks are often scaled during wafer/chip test testing to ensure performance, reliability, and functionality of the SoC at various operating conditions.

Fig. 1: Scaling clock frequencies.

In some cases, the ATPG patterns are generated using a single time domain, in which the same ATE period generates all clock edges for the SoC under test. This means that extra test vectors are required for the slower clocks, increasing the use of tester memory. As previously noted, reducing the number of test vectors to fit into the available memory also reduces coverage, making it more likely that defects will go undetected.

Fig. 2: Separate time domains.

The better approach is for the tester to handle each time domain as a separate test pattern, with each pattern running concurrently starting at the same time. Not forcing slow clocks to align with faster clocks reduces the number of test vectors and optimizes test memory utilization. This enables higher coverage for a given memory size. However, switching to multiple time domains poses some challenges:

  1. Performance issues when switching from one time domain to another
  2. Suboptimal vector memory utilization as each vector triggers values for each pin

To address such challenges, the test software must support multiple time domains and generate multiple test pattern files with pins partitioned based on the time domain. Doing so will help optimize vector memory by using repeats and loops for various modes.

Such a solution is provided by Synopsys TestMAX Vtran, a vector translation program that reads patterns and results from automatic test pattern generation (ATPG) and simulation tools and then converts them to popular automated ATE and simulator formats. A configuration (config) file specifies the test period, pattern file name, pin configuration, and tester format for each pattern file. TestMAX Vtran will align the cycles to ensure functionality and generate multiple output files with appropriate pin partitioning based on time domain.

Fig. 3: Synopsys Vtran ATPG to ATE flow.

This is known as the ATPG-to-ATE translation flow, with the main goal of creating high fault-coverage test vectors. In addition to generating the revised pattern files, Synopsys Vtran also generates a simulation testbench to run the test vectors and verify that they yield the expected results. This double-checks the accuracy of the config file and ensures that the vectors will run properly on the ATE. A graphical user interface (GUI) is included for ease of use and a waveform database is created for debug purposes.

In addition to ATPG test vectors, many test patterns include vectors extracted from functional simulation of the SoC design. The simulation-to-ATE translation flow supports this process, reading common simulator result formats such as value change dump (VCD) and generating the test patterns. The VCAP utility extracts a variety of useful information from the simulation, including setup times, edge timing, signal glitches, and statistical analysis. Again, a testbench is generated and used to run and validate the test vectors.

Both flows include additional test memory optimization with repeats, loops, smart analysis of vectors, exploration of varying window sizes, and compression. The effectiveness of this novel approach was demonstrated in a case study reported by users at a recent Synopsys Users Group (SNUG) event. They selected a combination of tests, including TAP, scan, and built-in self-test (BIST), running on two asynchronous clocks: TAP at 10ns and non-TAP at 5ns. This meant that a single time domain test had to run at a 5ns period with both clocks synchronous.

Fig. 4: Synopsys Vtran multi-time domain test pattern files.

As shown in the table above, using Synopsys Vtran to generate multi-time domain test pattern files with asynchronous clocks dramatically reduced the amount of vector memory required. The savings ranged from 41% to nearly 50% depending upon the mix of tests, with no loss of coverage. The resulting text vectors were validated as ready to use on ATE. The users concluded that the flow was solid and could be extended to other formats and other testers that support multiple time domains.

As this case study shows, taking advantage of the multi-time domain capabilities of modern ATE brings enormous advantages in maximizing production test coverage while minimizing pattern memory. Synopsys TestMAX Vtran provides an automated way to achieve these goals with minimal setup requirements. It is certified per the ISO 26262 standard for safety-critical automotive applications. It is part of a seamless test flow with other Synopsys solutions, but it supports other ATPG and simulation tools for wide industry applicability.

Production test for complex SoC designs is getting harder all the time, and multiple time domains can help meet several of the key challenges. For more information, see and

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