3D Stacked HBM and Accelerators for LLMs: Heat Management and PDN (Georgia Tech, SK Hynix)


A new technical paper titled "3D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency" was published by a researcher from Georgia Institute of Technology and SK Hynix. Abstract "Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures such as 2.5D integration of... » read more

Chip Industry Technical Paper Roundup: Oct. 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=482 /] Find more semiconductor research papers here. » read more

AI-Empowered Analog IC Sizing Methods (Univ. of Glasgow Et Al.)


A new technical paper titled "From Systematic to Intelligent: Assessing AI-Empowered Optimization Techniques for Analog Building Block Sizing" was published by researchers at University of Glasgow, Mediatek, The University of Edinburgh, Magics Technologies NV, University of Sevilla and Georgia Institute of Technology. Abstract "This paper presents a comprehensive, design-insight-based compa... » read more

Wafer Warpage Evolution During Key Backside Power Delivery Network Fabrication Steps (Korea Univ., Georgia Tech)


A new technical paper titled "Process-Induced Warpage Behavior in Backside Power Delivery Network Fabrication" was published by researchers at Korea University and Georgia Institute of Technology. Abstract "As semiconductor devices continue to scale, backside power delivery networks (BSPDNs) have emerged as a promising alternative to conventional front-side power delivery networks (FSPDNs),... » read more

Chip Industry Technical Paper Roundup: Sept 23


New technical papers recently added to Semiconductor Engineering’s library: [table id=478 /] Find more semiconductor research papers here. » read more

KAN Acceleration: Algorithm Hardware Co-Design Approach (Georgia Tech, National Tsing Hua Univ., TSMC)


A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems" was published by researchers at Georgia Institute of Technology, National Tsing Hua University and TSMC. Abstract "Recent developments have introduced Kolmogorov-Arnold Networks (KAN), an innovative architectural paradigm capable of replicating conventional deep neural network (DNN... » read more

Chip Industry Technical Paper Roundup: Sept 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=471 /] Find more semiconductor research papers here. » read more

Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)


A new technical paper titled "OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs" was published by researchers at Georgia Institute of Technology. Abstract "High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential language like ... » read more

Chip Industry Technical Paper Roundup: Sept 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=469 /] Find more semiconductor research papers here. » read more

A Comparative Study With Horizontal and Verticals FETs (POSTECH, Georgia Tech)


A new technical paper titled "Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET" was published by researchers at POSTECH and Georgia Institute of Technology. Abstract "For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of hori... » read more

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