Sub-3nm backside clock and signal routing; 3D stacked HBM for LLMs; microarchitectural side-channels; Ga-based SMP for Cu-to-Cu bonding; wafer defect patterns; advanced packaging roadmap 2.0; monolithic 3D stackable DRAM; HW for disaggregated LLM inference; zero-knowledge proofs on GPUs.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling | University of Texas at Austin, Intel |
| 3D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency | Georgia Institute of Technology, SK Hynix |
| Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking | Duke University, Harvard University, University of Florida |
| Sonochemical Synthesis of Submicrometer Ga-Based Particles for Cu-to-Cu Interconnection | National Cheng Kung University |
| DECOR: Deep Embedding Clustering with Orientation Robustness | Oregon State University, Micron Technology |
| Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap 2.0 | SRC |
| Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving | UC San Diego, Georgia Tech, University of Illinois Urbana-Champaign, Illinois Institute of Technology |
| SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference | Princeton University, University of Washington |
| ZKProphet: Understanding Performance of Zero-Knowledge Proofs on GPUs | University of Michigan |
Find more semiconductor research papers here.
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