Chip Industry Technical Paper Roundup: Oct. 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=484 /] Find more semiconductor research papers here. » read more

Grouping Complex Wafer Defect Patterns Into Meaningful Clusters (Oregon State Univ., Micron)


A new technical paper titled "DECOR: Deep Embedding Clustering with Orientation Robustness" was published by researchers at Oregon State University and Micron Technology. Abstract "In semiconductor manufacturing, early detection of wafer defects is critical for product yield optimization. However, raw wafer data from wafer quality tests are often complex, unlabeled, imbalanced and can conta... » read more

Chip Industry Week in Review


SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Chip Industry Technical Paper Roundup: July 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=426 /] Find more semiconductor research papers here. » read more

Analytical Methods For Analyzing PFAS In Semiconductor Wastewater (Oregon State University)


A new technical paper titled "Practical Guidance on Selecting Analytical Methods for PFAS in Semiconductor Manufacturing Wastewater" was published by researchers at Oregon State University, Corvallis. Abstract "The focus of this review is to provide an overview of the nomenclature, structure, and properties of perfluoroalkyl and polyfluoroalkyl substances (PFAS) that dictate the selection o... » read more

Research Bits: May 13


Benchmarking 3D-IC cooling Researchers from Massachusetts Institute of Technology (MIT) and HRL Laboratories developed a specialized chip to test and validate cooling solutions for packaged chip stacks. The chip dissipates extremely high power, generating heat through the silicon layer and in localized hot spots to mimic high-performance logic chips. It then uses diodes to measure temperatu... » read more

Research Bits: Apr. 29


Microchannels for two-phase cooling Researchers from the University of Tokyo propose cooling chips using microchannels built into the chips themselves. The method utilizes microfluidic channels to create a capillary structure through which coolant flows and a manifold distribution layer that controls the distribution of coolant. The structure enabled two-phase cooling through better managem... » read more

Liquid-Infused Nanostructured Composites As A Universal Thermal Interface Solution for Cooling Applications


A new technical paper titled "Liquid-infused nanostructured composite as a high-performance thermal interface material for effective cooling" was published by researchers at Carnegie Mellon University, Oregon State University and Arieca. Abstract "Effective heat dissipation remains a grand challenge for energy-dense devices and systems. As heterogeneous integration becomes increasingly inev... » read more

Research Bits: Jan. 7


Deep UV microLED for maskless lithography Researchers from the Hong Kong University of Science and Technology, Southern University of Science and Technology, and the Suzhou Institute of Nanotechnology developed an aluminum gallium nitride deep-ultraviolet microLED display array for maskless lithography.  They also built a maskless lithography prototype platform. "The team achieved key brea... » read more

Chip Industry Technical Paper Roundup: Nov. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=386 /] » read more

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