Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Chip Industry Week in Review


The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

Manufacturing Bits: Oct. 12


MoSi2 pellicles for EUV Hanyang University has presented a paper that describes a novel molybdenum disilicide (MoSi2) pellicle membrane for use in extreme ultraviolet (EUV) lithography. With a 28nm thickness, a MoSi2 membrane has demonstrated a 89.33% transmittance for EUV lithography. The pellicle technology is still in R&D. MoSi2, which is a silicide of molybdenum, is a refractory cer... » read more