Chip Industry Week In Review


IBM unveiled a 7Å transistor architecture that uses staggered nanosheet transistors stacked on a precisely beveled angle, almost like tiles on a roof. That allows more transistors to be crammed into a given area, boosting performance by 50% or power efficiency by up to 70%. Perhaps even more important, IBM claims a 40% improvement in SRAM scaling, which is orders of magnitude faster and lower ... » read more

Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Microelectronics and Advanced Packaging Technologies Roadmap 2.0 (SRC)


The Semiconductor Research Corporation just released its Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap 2.0, a comprehensive update to the industry’s first 3D semiconductor roadmap. The roadmap includes contributions of over 370 experts from 132 organizations, with updated content and a new chapter on digital twins and their applications. The roadmap was funded by the ... » read more