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AI-Based Method to Prune the Design Space of Heterogeneous NoCs


Abstract "Often suffering from under-optimization, Networks-on-Chip (NoCs) heavily impact the efficiency of domain-specific Systems-on-Chip. To cope with this issue, heterogeneous NoCs are promising alternatives. Nevertheless, the design of optimized NoCs satisfying multiple performance objectives is extremely challenging and requires significant expertise. Prior works failed to combine many... » read more

A Comparative Analysis of Computer-Aided Design Tools for Complex Power Electronics Systems


Abstract: "Companies working on semiconductors must currently assure the customers of not only the performance of the semiconductor device per se, but also its performance when it is implemented in a real board, therefore including the role of parasitic effects. It is therefore very important to evaluate, especially during the design phase, not only the single device, but the complete board ... » read more

RF And Microwave Solid-State Power Amplifiers Design Is A Speciality


In the world of RF and microwave engineering, the design and development of solid-state amplifiers is a specialty. It has always required many years of specialized engineering experience and a suitable collection of test and measurement equipment. While these will always be necessary, to be successful in the marketplace today, it is also essential to use a combination of specialized and general... » read more

Best Practices for Deploying ClioSoft SOS7 on AWS


Semiconductor integrated circuits (ICs) are at the center of a number of modern technological innovations. To keep up with the ever-increasing pace of innovation, IC design teams require robust, scalable design management (DM) solutions to enable seamless global collaboration and to increase productivity. This paper outlines the advantages of and best practices for deploying the ClioSoft SOS de... » read more

10nm And 7nm Routability – How Is Your CAD Flow Doing?


At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs - Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero Castagnetti, Distinguished Engineer, Broadcom Limited. This topic is of course extremely broad, but it was interesting getting fee... » read more