tag: memory architecture

Shift-left Schematic Memory Contention Analysis
By Siemens EDA - 11 Jun, 2026 - Comments: 0

Insight Analyzer streamlines memory block design by enabling early detection of memory contention at the schematic level. This shift-left approach lets design teams optimize architectures, mitigate risks and address reliability concerns before layout and manufacturing, helping to avoid costly rework and delays. Designers gain actionable analysis and clarity for complex memory block structures, ... » read more

Overview of ALD-Driven Oxide Semiconductors for High Density, Low Power Memory Architectures (Hanyang Univ., imec)
By Technical Paper Link - 25 Jan, 2026 - Comments: 0

A new technical paper titled "Oxide Semiconductor for Advanced Memory Architectures: Atomic Layer Deposition, Key Requirement and Challenges" was published by researchers a Hanyang University and imec. Abstract "Oxide semiconductors (OSs), introduced by the Hosono group in the early 2000s, have evolved from display backplane materials to promising candidates for advanced memory and logic ... » read more

LtRAM And StRAM: Specialized Memory Architectures Leveraging Workload-Specific Access Characteristics (Stanford, Microsoft)
By Technical Paper Link - 12 Aug, 2025 - Comments: 0

A new technical paper titled "Towards Memory Specialization: A Case for Long-Term and Short-Term RAM" was published by researchers at Stanford University and Microsoft, and an independent researcher. Abstract "Both SRAM and DRAM have stopped scaling: there is no technical roadmap to reduce their cost (per byte/GB). As a result, memory now dominates system cost. This paper argues for a parad... » read more

Evaluation of Cache Replacement Policies Using Various Typical Simulation Approaches
By Technical Paper Link - 06 Feb, 2024 - Comments: 0

A technical paper titled “Improving the Representativeness of Simulation Intervals for the Cache Memory System” was published by researchers at Complutense University of Madrid, imec, and KU Leuven. Abstract: "Accurate simulation techniques are indispensable to efficiently propose new memory or architectural organizations. As implementing new hardware concepts in real systems is often not... » read more

CXL: The Future Of Memory Interconnect?
By Karen Heyman - 12 Oct, 2023 - Comments: 1

Momentum for sharing memory resources between processor cores is growing inside of data centers, where the explosion in data is driving the need to be able to scale memory up and down in a way that roughly mirrors how processors are used today. A year after the CXL Consortium and JEDEC signed a memorandum of understanding (MOU) to formalize collaboration between the two organizations, suppor... » read more

MRAM Getting More Attention At Smallest Nodes
By Karen Heyman - 10 Aug, 2023 - Comments: 2

Magneto-resistive RAM (MRAM) appears to be gaining traction at the most advanced nodes, in part because of recent improvements in the memory itself and in part because new markets require solutions for which MRAM may be uniquely qualified. There are still plenty of skeptics when it comes to MRAM, and lots of potential competitors. That has limited MRAM to a niche role over the past couple de... » read more

A PIM Architecture That Supports Floating Point-Precision Computations Within The Memory Chip
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications” was published by researchers at Rochester Institute of Technology and George Mason University. Abstract: "Processing-in-Memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learnin... » read more

Automated Tool Flow From Domain-Specific Languages To Generate Massively Parallel Accelerators on HBM-Equipped FPGAs
By Technical Paper Link - 12 Apr, 2023 - Comments: 0

A new technical paper titled "Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics" was published by researchers at Politecnico di Milano and TU Dresden. The paper states "In this article, we propose an automated tool flow from a domain-specific language for tensor expressions to generate massively parallel acceler... » read more

Emulation System for Racetrack Memories Based on FPGA
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A technical paper titled "ERMES: Efficient Racetrack Memory Emulation System based on FPGA" was written by researchers at University of Calabria and TU Dresden. "This paper presents a new emulation system for RTMs based on heterogeneous FPGA-CPU Systems-on-Chips (SoCs). Thanks to its high flexibility, the proposed emulator can be easily configured to evaluate different memory architectures. ... » read more

A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password
By Technical Paper Link - 31 Mar, 2021 - Comments: 0

Abstract "For the first time, we proposed a 2T complementary architecture of one-time-programmable memory (OTP) in a foundry logic CMOS chip. It was then used to realize the PUF (Physical unclonable function), and the combination with the AI technology to provide a one-time password capability. At first, an OTP was developed based on a novel 2T CMOS unit cell. The experimental results show t... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy