Trading Off Power And Performance Earlier In Designs


Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Reducing Software Power


With the slowdown of Moore's Law, every decision made in the past must be re-examined to get more performance or lower power for a given function. So far, software has remained relatively unaffected, but it could be an untapped area for optimization and enable significant power reduction. The general consensus is that new applications such as artificial intelligence and machine learning, whe... » read more

Making Outdoor Lighting More Efficient, Safe, and Affordable With Open-Standard Control Networking Technology


By Echelon (Adesto) Modern commercial outdoor lighting systems are being asked to do more than ever before. In addition to fulfilling their primary purpose of casting light onto dark roadways, parking areas, and public spaces, outdoor lighting systems are increasingly evaluated for how well they reduce energy consumption, improve safety for both pedestrians and drivers, and serve as the founda... » read more

In-Memory Computing


Gideon Intrater, CTO at Adesto Technologies, talks about why in-memory computing is now being taken seriously again, years after it was first proposed as a possible option. What's changed is an explosion in data, and a recognition that it's too time- and energy-intensive to send all of that data back and forth between memories and processors on the same chip, let alone to the cloud and back. On... » read more

Why Chips Are Getting Noisier


In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Waiting For Chiplet Interfaces


There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

Case Study—RF ASIC Validation Of A Satellite Transceiver


ASIC validation in the RF world comes with its own set of hurdles and challenges, with high-quality lab equipment, experience and know-how essential. A recently completed RF sub-system validation at S3 Semiconductors is presented in the form of a case study of the execution. The validation PCB design focussed on impedance matching and shielding RF signals from noise sources. We built up an effi... » read more

Data Confusion At The Edge


Disparities in pre-processing of data at the edge, coupled with a total lack of standardization, are raising questions about how that data will be prioritized and managed in AI and machine learning systems. Initially, the idea was that 5G would connect edge data to the cloud, where massive server farms would infer patterns from that data and send it back to the edge devices. But there is far... » read more

Crossover To Memory Expansion With Adesto EcoXiP and NXP’s i.MX RT Crossover Processors


The ‘Crossover Processor’ integrates attributes of a microprocessor such as higher CPU speeds, multimedia interfaces and expandable memory into a microcontroller form factor built for cost effectiveness and fastest development time. This new crossover processor class of device provides embedded developers the ability to solve many problems in today’s fast-moving technology markets. To ... » read more

Power/Performance Bits: Jan. 22


Efficient neural net training Researchers from the University of California San Diego and Adesto Technologies teamed up to improve neural network training efficiency with new hardware and algorithms that allow computation to be performed in memory. The team used an energy-efficient spiking neural network for implementing unsupervised learning in hardware. Spiking neural networks more closel... » read more

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