Week In Review: Design, Low Power

Galaxy Semiconductor re-establishes with asset buy from Mentor; DO-254 tool qualification; Synopsys-Arm deal; superconducting electronics design.


Galaxy Semiconductor re-established with the planned acquisition of the Quantix Business assets from Mentor, a Siemens business. The software products Galaxy is acquiring focus on yield optimization, device characterization, and reliability improvement. Galaxy was initially founded in 1998; the Galway, Ireland-based company was then acquired by Mentor Graphics in 2016. The re-established company will be based in Menlo Park, CA and include previous founder Philippe Lejeune as Board Chairman and CTO. The deal is expected to close in a few weeks; terms were not disclosed.

Dialog Semiconductor completed its acquisition of Adesto Technologies. The deal is valued at $12.55 per share, approximately $500 million. Founded in 2006 and based in Santa Clara, CA, Adesto provides application-specific semiconductors, embedded systems, and specialty memory for IoT and industrial IoT applications.

Aldec added a customizable tool qualification data package to its ALINT-PRO verification tool for projects requiring Design Assurance Levels (DAL) A and B under DO-254 guidance. The package can prove ALINT-PRO can enforce the user’s chosen coding standard, either the one included or one the user has mapped into the tool. It also includes an automated test suite and comprehensive documentation.

Deals & People
Synopsys and Arm inked a multi-year agreement in which the two companies will jointly develop and distribute optimized Synopsys product reference methodologies to Arm customers and deliver training on the use of Synopsys products and flows with Arm IP. Synopsys will receive early access to certain Arm IP.

Synopsys will license digital synthesis technologies from EPFL as part of its participation in IARPA’s SuperTools project. In this project, Synopsys, University of Rochester, and Yokohama National University are developing a complete digital circuit design flow for Superconducting Electronics (SCE). The EPFL tool, developed by its Integrated Systems Laboratory, may reduce the power requirement of chips by mapping out logic flows in a way that reduces the number of logic steps needed to execute a given task.

Dr. Alessandra Nardi has been awarded the 2020 Marie R. Pistilli Women in Electronic Design Award. Nardi is the software engineering group director at Cadence and has worked on automotive methodologies with an emphasis on functional safety and reliability. Nardi developed a patent for the automatic design and verification of safety-critical electronic systems, and she managed cross-functional collaborations on the development of a functional safety flow for digital, analog, and mixed-signal SoCs for semiconductor and system companies. Additionally, Nardi is the chair of the Accellera Functional Safety Working Group and serves on the industrial advisory boards of ACM SIGDA and at Wayne State University.

Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead?

The Hardwear.io Security Conference is a digital event this year, with two upcoming webinars. Fault injection attacks on IoT devices will be discussed on July 6 at 6 PM CEST (9 AM PDT), and why hardware boundaries define platform security will feature July 30 at 7 PM CEST (10 AM PDT).

DAC will be a virtual event this year. It will still take place July 19 – 23, 2020. Watch what’s new in this year’s content and focus. Keynotes for the event will cover a system look at semiconductor technology, the RISC-V revolution, wafer-scale deep learning accelerators, and looking ahead to 6G.


Ryan Dean says:

Some more info on Superconducting Electronics would be welcome.. we’ve been waiting since the invention of the Cryotron!

Leave a Reply

(Note: This name will be displayed publicly)