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3D Power Delivery

The design of the power delivery network just got a lot more complicated, and designers can no longer rely on margining when things become vertical.

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Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels.

The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emphasis on lowering the voltage in any device connected to a battery.

“People design huge chips and they are dropping the voltage supply and increasing the frequency,” says Jerry Zhao, product management director at Cadence. “The power grid is under a considerable challenge to be strong enough to support the circuitry, but not overly designed so that you waste a lot of real estate. The challenge is how will the power delivery network (PDN) provide enough effective voltage supply to every instance so that my function will not change and my timing will not change. In the long run I also want to ensure that electromigration will not kill me reliability-wise.”

Stacking chips adds a new layer of complexity. “Unlike monolithic designs with power delivery from the package substrate only, 2.5D or 3D designs have additional silicon material, such as an interposer, in the power delivery path,” says Prasad Subramaniam, vice president for AI platform infrastructure at eSilicon. “Additional silicon material implies tighter budgets for power delivery from die, as well as the interposer and package substrate.”

More nodes, more complexity, but tighter requirements demand new approaches. “With the addition of 2.5D and 3D, there are a lot more transistors to deal with, a lot more power grid to deal with and a lot more nodes in the analysis to deal with,” says Chris Ortiz, principal application engineer at ANSYS. “With some of the newer technologies you are really getting into very low threshold voltages, so core power may be less that 1V. The power demand has not reduced, so in terms of power density it has probably gone up. It is very hard to put something together if you do separate margining. You need to analyze everything together and to know what the overall effect is going to be. The window for over-design is getting smaller and smaller and almost non-existent.”

Going vertical
There are many reasons to adopt vertical die stacking, but they can both help and hinder the design of the PDN. “In some cases, careful use of 3D technologies can make power better, but when those options are not available it also can make things worse,” says John Ferguson, director of marketing for Calibre DRC Applications at Mentor, a Siemens Business. “Consider, for example, traditional high-bandwidth memory (HBM). By vertically stacking, components are closer together, and therefore it is easier to get power to them. Also, historically the HBM would be placed on top of a substrate placed horizontally next to logic. This long electrical distance causes power concerns. By stacking the HBM on top of logic as with PoP design, power is significantly reduced. But, of course, stacking is not always an option.”

Gains in one area enable changes in others that can exacerbate power problems. “With the memories now so close to the logic chip, there are no limitations in the I/O performance that is holding back the processor,” says ANSYS’ Ortiz. “That means that the processors now can process a lot more information, and, in that respect, a lot more core power is coming into the design.”

Decoupling challenges
Decoupling capacitors traditionally have helped supply peak current demands. “Both the design and validation of the power delivery have their challenges,” says eSilicon’s Subramaniam. “They often require extensive use of decoupling capacitors on the package to ensure that clean power is delivered to all the chips in this multi-chip environment.”

An interposer helps with that. “When they are separated by some distance, such as when an interposer is used, you can put some decap on it and there are techniques you can use to isolate one die from another,” explains Ortiz. “In the 3D stacked environment, you really are not going to be able to do much to isolate each die when talking about the PDN, so if there is a high current demand it will be pulling charge form the other chips or essentially inducing a voltage noise in the other chips. So you do have to concern yourself with the amount of power the other chips will consume and how it may interfere with another chip that may be running off the same supply.”

Package complications
Many issues become more complex at the package level. “The power delivery needs to be robust to minimize the EMIR (electromagnetic and IR) drop,” says Subramaniam. “These designs are usually complex and may consume power in the hundreds of watts.”

But pin counts remain fixed. “With complex SoCs there are many different power domains, for example, for memory, core and I/O,” says Andy Heinig, acting Head of Department at Fraunhofer EAS. “But in the case of 2.5 and 3D integration, the number of different voltages would increase even more. On the other side, the number of package balls doesn’t increase in the same way so that the number of balls per supply voltage is decreasing.”

Routing is always a problem. “The power mesh competes for the same resources that are needed for routing,” adds Subramaniam. “Optimizing via placement allows us to minimize the resource requirements of the power mesh while maintaining its robustness.”

Arm recently taped out a prototype test-chip on GlobalFoundries’ 12nm FinFET process. “The power delivery network design (PDN) was a key consideration from the beginning of the design phase,” says Greg Yeric, fellow in Arm’s Research & Development Group. “In a two-stack 3D-IC design, power gets delivered through C4 bumps on the back-side of the bottom die, through TSVs and then through the entire metal stack to both dies (bottom and top). Not only does the PDN need to mitigate the intrinsic variation of instance voltage drop between the dies but it also has to be co-designed with the 3D signal routing since there is a direct trade-off between a robust power delivery network and high bandwidth signaling. Another key design consideration is 3D floor-planning to avoid placing high performance (and hence, higher power) blocks on the same X-Y location in separate 3D tiers because that will stress the power delivery TSVs as well.”

Increased thermal impact
Heat has been an issue for some dies, and stacking provides less opportunity for heat to escape, which makes analysis more difficult and more concerning. “When you put dies on top of each other, you have to analyze the thermal impact,” says Cadence’s Zhao. “The power grids, which carry so much current, create heat, which causes temperature to rise. Leakage increases with temperature, and that cause more current to be drawn. So is my power grid strong enough electrically? And is my power grid strong enough thermally to sustain its function as temperature rises?”

When stacking dies, engineering teams may not have all of the design data for dies that comes from third parties. “Given how close they are to each other, you will need to know a lot about the current demand and thermal hotspots in each chip,” warns Ortiz. “That requires some modeling, where you need to worry about the overall power coming out of the chip in a lumped thermal property. And you need a more accurate model that accounts for the distribution of power in the chip and allows you to take into account the thermal and PDN. So you must have access to the actual design data in an IP-neutral kind of way.”

But that is not the end of the thermal issue. “Electrical and thermal have different time constants. The simulation of vector sets is nanoseconds, but for thermal we have to consider milliseconds or seconds,” adds Zhao. “At the same time, the temperature has a different profile, depending upon activity, meaning it has to be done with dynamic analysis.”

Some tried-and-true approaches no longer apply. “Estimation, in order to reach a stable voltage supply, doesn’t work anymore,” says Fraunhofer’s Heinig. “The only way to ensure a stable power supply is through extensive use of simulation tools to see the behavior of the supply voltage. Tools can be used for the parasitic extraction and simulation, but major problems arise because of the need for data transfer between the tools. One solution to overcome the problem is the use of an Assembly Design Kit (ADK), like the one from Fraunhofer IIS/EAS, in which the data transfer between different tools of different vendors is implemented.”

Extraction issues
Simulation relies on accurate extraction, but that also has become more complicated. “In a simple one die chip, the parasitics we are most concerned about is resistance, which is very important on the chip, and capacitance,” Ortiz explains. “Inductance is not a huge factor. So there are a host of extraction and analysis techniques that enable you to analyze the chip and focus on resistance and capacitance, and which can handle the large number of nodes involved. When you bring in the package, the most relevant parasitic is inductance, a little bit of capacitance, but lesser so resistance. You are analyzing those parasitics, and the different resonance issues that come into play. When you bring in an interposer, you are sort of at an in-between stage. All of the parasitics come into play and they all have some relevance. All of the extraction techniques need to come into play to extract these parasitics for both the chip side, the interposer — where you need some new techniques for extracting all of the relevant parasitics — and the package and board side.”

3D adds one more complication. “Through-silicon vias (TSVs) are a unique extraction problem,” says Ortiz. “In the world of conductors and dielectrics, the TSV is surrounded by semiconductors — so it is a little different in terms of what you need to concern yourself with in terms of extraction.”

And this is no longer confined to a single technology. “When you add a silicon interposer or a 3D structure, and you have dies or layers on top of each other, those die may be on different process nodes and tools need to be able to support that,” says Zhao. “The extraction deck, the library deck, the timing, how you consider the boundary conditions of each die when they are either sitting next to each other or on top of each other — the first question is, can you analyze this?”

Finding resonances becomes even more important. “There are now so many activities and so many resonances within the system that it may lead to some questions or issues,” adds Ortiz. “When you have 2.5D, you have more chips involved, you have memory, you have the big chip itself. So you have to deal with more frequencies and more possible resonances, because you can think of each chip as a lumped RC, and you have more lumped RCs on a given inductive network. That creates a lot more potential resonances.”

Chiplet complications
Chiplets are increasingly being seen as a potential way to facilitate complex 2.5D and 3D designs, but they add some complications and limitations. “If you don’t own the entire design, you will need accurate models for each of the chiplets in terms of their power demand,” says Ortiz. “What is the passive nature of the chip? What about the activity of the chip? What are the current demands? All of these cannot be put into crude spreadsheet forms anymore. You need to have this in a simulation. You need to be able to lay it out, extract it, and understand what everything is doing. When there are a lot of companies providing each of the parts, you will need to be able to model the system. And you will need an environment that will be able to stitch everything together and do a full analysis, plus all of the variations, to get a robust picture of the PDN and to be able to determine if it can handle the complete system.”

That requires a different way of thinking. “I want to analyze how my chip behaves if it is hooked up to a chip produced by someone else,” says Zhao. “It provides a loading effect. Things like resonance or anything that creates interference between them can be fixed within your chip, but you may not be able to touch the other one. That creates some new limitations in the flow.”

Design in a 2.5D and 3D world is causing a convergence of many issues and all of them impact the power delivery network. Power has to be analyzed in terms of the power itself and, in addition, signal integrity and thermal integrity. For chiplets to become pervasive, new models are required.

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1 comments

BILL MARTIN says:

This has been solved by Prof. Swaminathan from Georgia Tech and is a patent owned by E-System Design. Any type of 3D structure (TSV, ball, pillar, etc) can be accurately modeled in a ‘sea’ of other 3D interconnections to understand cross talk as well as PDN issues. Given the ‘extraction’ and analysis used, it is not limited to small arrays.

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