The AI Server Challenge: Testing Power At Scale


Artificial intelligence is most often framed as a story of compute advancements. Faster GPUs, denser accelerators, and advanced process nodes. But behind every AI workload, the most fundamental constraint is power. Fig. 1: AI server market. Source: Grand View Research As AI servers scale to meet data center demand, power delivery is becoming one of the most critical and complex engine... » read more

PDN Challenges In DRAM-Based Compute-In-Memory Systems (UT Austin)


A new technical paper, "A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM," was published by researchers at UT Austin. Abstract "Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, matu... » read more

Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs


Power delivery has become one of the defining challenges of next-generation semiconductor systems. As AI, high-performance computing, and data-centric workloads drive higher performance and tighter integration, traditional 2D SoC design approaches are reaching their limits. The industry’s shift toward 2.5D and 3D heterogeneous integration promises breakthroughs in performance and efficiency�... » read more

Voltage Regulation Moves Into The Package


Integrated circuits require a variety of voltages and a wide range of currents, typically supplied by voltage regulators. But increasing power density is resulting in higher power delivery losses. Moving those regulators closer to the chips they power can reduce those losses. Co-packaging them holds the most promise, but it comes with challenges. “What people have been talking about, ev... » read more

Lines Blurring Between Supercomputing And HPC


Supercomputers and high-performance computers are becoming increasingly difficult to differentiate due to the proliferation of AI, which is driving huge performance increases in commercial and scientific applications and raising similar challenges for both. While the goals of supercomputing and high-performance computing (HPC) have always been similar — blazing fast processing — the mark... » read more

Top Tech Videos Of 2024


In 2024, hot topics included challenges involving chiplets and heterogeneous integration, AI, data management, MCUs, power semis, software-defined vehicles, sensors, adaptive test, yield tracking, safety monitoring, security, and much more. Top 5 most watched videos in 2024: Overlay Optimization In Advanced IC Substrates How To Stop Row Hammer Attacks What’s Changing In DRAM ... » read more

Power Delivery Challenged By Data Center Architectures


Processor and data center architectures are changing in response to the higher voltage needs of servers running AI and large language models (LLMs). At one time, servers drew a few hundred watts for operation. But over the past few decades that has changed drastically due to a massive increase in the amount of data that needs to be processed and user demands to do it more quickly. NVIDIA's G... » read more

The Seven Pillars Of IC Package Physical Design


Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

An Inside Look At Testing’s Leading Edge


Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. SE: How does test change with AI chips, where you've got massive numbers of accelerators and processors developed at 7 and 5nm? Slessor: A lot of the AI stuff that we've been... » read more

3D Power Delivery


Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

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