Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs

Power delivery has become one of the defining challenges of next-generation semiconductor systems. As AI, high-performance computing, and data-centric workloads drive higher performance and tighter integration, traditional 2D SoC design approaches are reaching their limits. The industry’s shift toward 2.5D and 3D heterogeneous integration promises breakthroughs in performance and efficiency—but it also introduces unprecedented power integrity (PI) complexity.

In modern multi-die architectures, power delivery is no longer confined to a single chip. Instead, it spans stacked dies, interposers, bridges, and packages connected by thousands of micro-bumps and TSVs. Small disturbances—voltage droop, simultaneous switching noise (SSN), or impedance resonances—can cascade across the stack, impacting performance, reliability, and yield.

Successfully managing PI in this environment requires more than isolated die- or package-level analysis. It demands a unified, system-level view that captures real switching behavior, high‑fidelity parasitics, and electromagnetic interactions across the entire power delivery network (PDN).

This article explores how Siemens’ Innovator3D IC solution suite enables comprehensive system-level power integrity analysis for 2.5D and 3D ICs—helping teams identify risks earlier, analyze faster, and sign off with confidence.

Why power integrity is harder in 3D ICs

1. Vertical power delivery changes everything

In 3D ICs, power delivery paths are deeply vertical. Stacked dies, dense micro-bumps, TSVs, redistribution layers (RDL), and shared return paths dramatically increase coupling and sensitivity to noise. Compared to planar designs, these structures amplify IR drop, L·di/dt noise, and cross-die interference. As voltage margins continue to shrink, these effects become first-order constraints that can determine system success or failure.

2. Fragmented flows increase risk

Despite the system-level nature of the problem, PI analysis is often fragmented across multiple point tools—one for die-level analysis, another for interposers, and yet another for package modeling. Engineers must manually move, stitch, and reconcile data across these tools. This disjointed approach increases errors, slows iteration, and often pushes system-level PI analysis late into the design cycle—when fixes are most expensive.

3. TSV extraction must scale

TSVs are a cornerstone of 3D integration, but they are notoriously difficult to model accurately. Traditional electromagnetic solvers rely on surface meshing techniques that do not align well with the cylindrical geometry of TSVs. The result is excessive unknowns, long runtimes, and poor scalability for TSV-rich designs.

A unified system-level power integrity approach

To address these challenges, a holistic, system-aware PI analysis flow is essential. The Siemens Innovator3D IC solution suite delivers an integrated PI workflow designed specifically for 2.5D and 3D IC architectures. It unifies system assembly, die-level power modeling, high‑fidelity interposer and TSV extraction, and broadband package electromagnetic analysis—into a single, automated flow.

The central cockpit

Innovator3D IC Integrator is at the center of this approach, serving as the system cockpit. It brings together all design elements—dies, interposers, bridges, and packages—into a single, consistent system model. By acting as a single source of truth, it ensures electrical connectivity, power-domain definitions, and bump assignments remain aligned throughout the analysis flow.

From within this unified environment, engineers can:

• Visualize power distribution across the full 2.5D/3D stack
• Select specific power domains or VDD rails for analysis
• Eliminate manual data stitching and set up

Once a network is selected, Innovator3D IC Integrator automatically orchestrates high‑fidelity extraction and simulation, creating a complete system-level PI testbench in HyperLynx SI/PI.

Fig. 1: System-level power integrity flow using Innovator3D IC Integrator.

Accurate modeling from die to package

Die-level power modeling

Accurate system-level PI analysis starts with realistic die behavior. Siemens mPower generates detailed chip power models (CPMs) that capture both static and dynamic current consumption.

These models reflect workload-dependent switching behavior, enabling realistic prediction of voltage droop and SSN when the die is placed into the full system context. CPMs integrate cleanly with HyperLynx SI/PI, allowing system simulations to closely mirror real operating scenarios.

High-fidelity interposer and TSV extraction

In 2.5D and 3D ICs, interposers and bridges play a critical role in power delivery—and their parasitics cannot be approximated. Siemens’ Calibre xACT3D performs field-based RLCK extraction that accurately captures resistance, inductance, capacitance, and substrate coupling across TSVs, micro-bumps, RDLs, and routing layers.

Unlike traditional mesh-based solvers, Calibre xACT3D uses cylindrical basis functions (Bessel and Hankel functions) tailored to TSV geometry. This approach dramatically reduces the number of unknowns, enabling scalable extraction for dense TSV arrays without sacrificing accuracy.

Fig. 2: TSV modeling using cylindrical basis functions compared to traditional meshing.

Package-level electromagnetic analysis

A package often contributes a significant portion of total PDN impedance. Innovator3D IC Advanced Package Solvers provide broadband electromagnetic extraction to model plane capacitance, via inductance, trace coupling, and resonant structures using S-parameters.

These models capture frequency-dependent behavior from MHz to GHz, enabling designers to identify anti-resonance peaks, return-path discontinuities, and package-level noise amplification that can affect multiple dies simultaneously.

System-level simulation and insight

The final step in the flow is the automatic creation of a unified, system-level electrical netlist. Innovator3D IC Integrator seamlessly stitches together:

• CPMs from mPower
• RLCK extraction from Calibre xACT3D
• Package models from Innovator3D IC Advanced Package Solvers

This complete PDN is simulated in HyperLynx SI/PI, enabling engineers to evaluate:

• Worst-case SSN across multiple dies
• Dynamic voltage droop under real workloads
• Frequency-domain impedance and resonance behavior

With a single simulation environment, teams can quickly pinpoint weaknesses, optimize decoupling strategies, and assess trade-offs before costly design changes or fabrication.

Fig. 3: Test-bench sketch created within HyperLynx SI/PI.

Fig. 4: Normalized transient drop at VDD_die.

Automated, accurate, scalable PI analysis

As 2.5D and 3D IC designs continue to scale in complexity, power integrity can no longer be treated as a localized problem. A system-level view—spanning dies, interposers, and packages—is essential to ensure stable power delivery, predictable performance, and first-pass silicon success.

Our more complete treatment goes deeper into additional topics, including:

• Advanced TSV modeling theory
• Expanded extraction and solver methodologies
• Additional use cases and implementation details

To learn more, download the full paper and discover how system-level PI analysis can de-risk your next 2.5D or 3D IC design.

Sudarshan Deo is a software R&D manager for 3D IC at Siemens Digital Industries Software. Deo has expertise in implementing and integrating complex 3D IC workflows, including physical design, DFT, multi-physics, thermal, stress, SI, PI, DC IR-drop analysis, and advanced AI frameworks, and he serves as a technical point of contact for divisions across Siemens Digital Industries Software. Deo holds an M.S. in Computer Science from California State University, Sacramento.