Week In Review: Design, Low Power

eSilicon, Synopsys, Rambus add high-speed PHYs; Aldec’s FPGA partitioning; Moortec in-chip monitoring for 5nm; CXL VIP; chiplet design; Arm chiplets; TSMC certifications.


eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 24 channels per PHY with one redundant lane per channel to improve production yields. The part also supports built-in self-test (BIST), internal loopback and external PHY-to-PHY link tests. Standards supported include IEEE 1149.1 (JTAG) and 1149.6 (AC JTAG) boundary scan.

Aldec added automatic FPGA partitioning to its HES-DVM hybrid verification environment. The company says the new feature minimizes required interconnections and can take partitioning of FPGAs for prototyping down to minutes rather than days or weeks when done manually. The latest release also includes SyntHESer, a proprietary HDL compiler the company says outperforms third-party synthesizers, as well as Board Compiler, which is used to import files in the form of Verilog structural descriptions for third party boards that use Xilinx Virtex UltraScale devices.

Synopsys launched 112G Ethernet PHY IP on TSMC’s N7 process supporting true long reach channels for up to 800G networking applications. The IP delivers PAM-4 signaling for more than 35dB channel loss across optical, copper cables, and backplane interconnects. It allows placement of square macros in a multi-row structure and along all edges of the die and features a transmit phase-locked loop architecture for independent, per lane data rates for a broad range of high-throughput protocols and applications.

Moortec announced that its latest In-Chip Monitoring IP Subsystem is now available on TSMC’s N5 and N5P process technologies. The subsystem includes a process monitor for DFVS optimization and variability monitoring, a voltage monitor, a high precision low power junction temperature sensor, and a PVT Controller with AMBA APB interfacing.

Rambus taped out its 112G XSR (extra short reach) SerDes PHY on a leading-edge 7nm process node optimized for PPA to support data center, networking, HPC, AI and ML applications using die-to-die (D2D) and die-to-optical engine (D2OE) connections. It supports high-bandwidth connectivity greater than 800 Gbps per millimeter of beachfront and is targeted for low-power, high-speed applications with chip disaggregation, using 1 pJ/bit or 1mW/Gbps power. It complied with the OIF-CEI standard.

Flex Logix received working first silicon of its validation chip for the EFLX 4K eFPGA IP cores running on GlobalFoundries’ 12nm Leading-Performance (12LP) FinFET and 12LP+ platforms. The validation chip consists of 4 EFLX cores (2 DSP and 2 Logic, for a total of 14K LUT4s and 80 DSP MACs) with integrated RAM and is currently in characterization. EFLX evaluation boards on GF’s 12LP/12LP+ and 14nm Low Power Plus (14LPP) platform are now available.

Arm and TSMC debuted a 7nm silicon-proven chiplet system using multiple Arm cores with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging to demonstrate key technologies for HPC SoCs. It includes four Cortex-A72 processors, an on-die, bi-directional interconnect mesh bus operating at 4GHz, and a chiplet design methodology connected by an 8Gb/s inter-chiplet interconnect with scalable 0.56pJ/bit power efficiency and 1.6Tb/s/mm2 bandwidth density over a TSMC CoWoS interposer.

Spectral Design & Test launched new memory compilers targeted at 5G applications, including base stations and edge IoT. Joining the company’s existing Static RAMs & Register File compliers is UVT (Ultra Low Vt) MemoryIP in GlobalFoundries’ 45 RF SOI process, which targets edge AI applications and is designed to reduce leakage power in the range of 8 – 10X compared to the generic Standard Vt MemoryIP for base stations.

Avery Design Systems revealed Compute Express Link (CXL) VIP to support the latest CXL Specification 1.1. The VIP supports SystemVerilog/UVM host, device, PHY, and PIPE-to-PIPE box agents and models, extensive protocol checking, functional coverage, and a testsuite to ensure compliance.

Truechip debuted CXL VIP with support for all three CXL protocols and device types to meet specific application requirements. The VIP also supports ARB/MUX Link Management Packets (ALMPs) for power state transition requests, dynamic masking of error, and built-in test suites, sequences, checks and coverage for all link configurations up to 16 lanes and 32 GT/s data rates.

The MIPI Camera Serial Interface-2 (MIPI CSI-2) specification was updated. MIPI CSI‑2 v3.0 adds Unified Serial Link (USL) to encapsulate connections between an image sensor module and application processor, Smart Region of Interest (SROI) for analyzing images, inferencing algorithms and making better deductions, and RAW-24, for representing individual image pixels with 24-bit precision.

Rambus uncorked a portfolio of GDDR6, HBM2, and 112G LR (Long Reach) SerDes PHYs for next-generation data center, networking, wireless 5G, HPC, ADAS, AI and ML applications on TSMC’s N7 process.

TSMC Certifications
ANSYS’ Totem and RedHawk family of multiphysics solutions were certified on TSMC’s N5P and N6 process technologies. The certification includes extraction, power integrity and reliability, signal line electromigration (EM) and thermal reliability analysis for self-heat, thermal-aware EM and statistical EM budgeting analysis.

Cadence’s digital and signoff full flow and custom/analog tools were certified on TSMC’s N6 and N5/N5P process technologies for the latest DRM and SPICE. Digital and signoff tool enhancements include expanded EUV layer support and back end of line (BEOL) layer modeling and middle end of line (MEOL) features, while the custom/analog tools have an accelerated custom placement and routing methodology, universal polygrid snapping and color engine support features for N6, and expanded design rule constraint support. Corresponding PDKs are available now.

Mentor’s Calibre nmDRC, Calibre nmLVS, Calibre YieldEnhancer, Calibre PERC and Analog FastSPICE Platform have been certified for the latest version of DRM and SPICE on TSMC’s N5, N7+, N5P and N6 processes. YieldEnhancer added features in support of the latest TSMC technologies, including easier and simpler modification of fill shapes and last-minute ECO design changes. Additionally, Mentor’s Tanner S-Edit schematic capture tool and the Tanner L-Edit layout editor were certified for TSMC’s interoperable PDKs (iPDKs) for a broad range of TSMC specialty process technologies for high-volume analog IC designs.

Synopsys’ design tools were certified on TSMC’s N5P and N6 process technologies. A range of new features for HPC and mobile design flows were certified for the latest N5P DRM and SPICE, including new placement rules for spacing, abutment, and boundary cell insertion and low-leakage cell placement. Synopsys is also working with TSMC on a portfolio of DesignWare interface IP, logic libraries, embedded memories, and one-time programmable (OTP) non-volatile memory (NVM) IP on TSMC’s N5P Process.

Kandou raised $56 million in Series C funding, bringing total investment in the company to nearly $100 million. The investment will be used to scale all aspects of Kandou’s operations and to expand the development and deployment of its high speed, low power interconnect devices. Participating in the round was Bessemer Venture Partners, Columbia Lake Partners, Digital Transformation Fund, Fayerweather Capital Partners, Forestay Capital, Kreos Capital, Raging Capital, Swisscom Ventures, and Walden International.

Wave Computing has a new CEO, reports EE Times. Sanjai Kohli took the helm after the AI company’s former CEO, Art Swift, left in early September citing disagreement over short-term fundraising strategy. Kohli has been founder and CTO of numerous startups in the GPS and telecommunications fields, including SiRF, WirelessHome, TruSpan, and Inovi and is recognized as a major contributor to commercialization of GPS.

Check out upcoming industry events and conferences: ORConf for open source design will be Sept. 27-29 in Bordeaux, France. Next month, Arm TechCon will take place Oct. 8-10 at the San Jose, CA Convention Center. Also on Oct. 10 is the PCB Systems Forum 2019 – Milan in Milan, Italy. Later in the month, the System-on-Chip Conference will be at the University of California, Irvine on Oct. 16-17, while the 13th IEEE/ACM International Symposium on Networks-on-Chip will be held Oct. 17-18 in New York, NY.

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