MIPI Deployment In Ultra-Low-Power Streaming Sensors

Streams of data from higher-speed sensors pose throughput and latency challenges for designers. However, optimizing a design for those criteria can come at the expense of increased power consumption if not conceived and executed carefully. A device like a high-resolution, high-frame-rate home security camera in a non-wired application requiring frequent battery changes or recharging will likely... » read more

New Developments Set To Accelerate MIPI CSI-2 Adoption In Automotive

As Advanced Driver-Assistance Systems (ADAS) become more sophisticated, cars are equipped with an increasing number of cameras and sensors. To support features like automated parking, adaptive cruise control, and enhanced night vision, sensors source multiple wavelengths and deploy cameras with higher quality data formats, higher frame and refresh rates. ADAS systems are all powered by data sou... » read more

MIPI In Next Generation Of AI IoT Devices At The Edge

The history of data processing begins in the 1960’s with centralized on-site mainframes that later evolved into distributed client servers. In the beginning of this century, centralized cloud computing became attractive and began to gain momentum becoming one of the most popular computing tools today. In recent years however, we have seen an increase in the demand for processing... » read more


Building on the enormous design and manufacturing base which made high-resolution, miniaturized digital cameras possible for mobile phones, the universe of MIPI applications has expanded to the automotive world. Today’s cars, particularly with the increasing sophistication of Advanced Driver Assistance Systems (ADAS), are brimming with cameras, sensors, and displays. Park assist, driver monit... » read more

MIPI On Wheels: Enabling ADAS Applications

Formed in 2003, the Mobile Industry Processor Interface (MIPI) Alliance brought together leading system and chip companies to provide standards for the essential video interface technologies for cameras and displays in phones. Over the years, the alliance has expanded its scope to publish specifications covering physical layer, multimedia, chip-to-chip and inter-processor communications (IPC), ... » read more

Week In Review: Design, Low Power

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more