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Week In Review: Design, Low Power


eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

Preparations for DAC


The 53rd DAC is just days away now and the program is pretty well established at this point. It is returning to Austin after a couple of years in San Francisco. In 2013 it was held in this location for the first time and there was a herculean effort to bring the local design community to the event. They did amazing well and while attendance fell slightly compared to the previous year in San Die... » read more