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Next Steps For Panel-Level Packaging


Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

New Patterning Options Emerging


Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Tennant’s Law


It’s hard to make things small.  It’s even harder to make things small cheaply. I was recently re-reading Tim Brunner’s wonderful paper from 2003, “Why optical lithography will live forever” [1] when I was reminded of Tennant’s Law [2,3].  Don Tennant spent 27 years working in lithography-related fields at Bell Labs, and has been running the Cornell NanoScale Science and Techno... » read more