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Next Steps For Panel-Level Packaging


Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

Week In Review: Manufacturing, Test


Semicon West news The Semicon West trade show opened this week with a hybrid in-person and virtual event. Several companies introduced new products or made announcements at Semicon. Some announcements coincided with the show. At Semicon, Lam Research introduced the Syndion GP, a new product that provides deep silicon etch capabilities to chipmakers developing next-generation power devices a... » read more

Manufacturing Bits: Aug. 24


Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more