Sorting Out Packaging Options

Experts at the Table, Part 1: Better naming conventions will reduce confusion over different packaging types, while cost, applications and standards will narrow the choices.


Semiconductor Engineering sat down to discuss advanced packaging with David Butler, executive vice president and general manager of SPTS Technologies; Ingu Yin Chang, senior vice president president at ASE Group; Hubert Karl Lakner, executive director of the Fraunhofer Institute for Photonic Microsystems; Robert Lo, division director for electronics and optoelectronics research at Industrial Technology Research Institute (ITRI); and Bahgat Sammakia, vice president of research at Binghamton University. What follows are excerpts of that conversation.

SE: The market is moving increasingly toward heterogeneous integration, otherwise known as disaggregation or dis-integration. But there are so many different options on the table that it’s hard to keep straight. How do we differentiate the different types of packaging?

Lakner: We prefer to look at all of these as 3D integration because it covers everything. It’s difficult to explain what is 2.5D (silicon interposer) or 2.1D (organic interposer). We need a lot of different approaches, and we need to tell the whole story. 3D heterogeneous integration covers all aspects that we will need in the future.

Chang: When we talk about 3D, the common definition is that it uses through-silicon vias. For us, everything between through-silicon vias and traditional packaging is 2.5D. Everyone is coming up with a different definition of what 2.5D is, but there’s no clear way of how to create that other than with through-silicon vias. There are different ways of doing it, whether it’s a fan-out solution or even a traditional MCM (multi-chip module) solution. You could do it one way or the other, but 2.5D does give you the freedom to create more options.

Fig. 1: 2.5D vs. 3D. Source: ASE/SPIL

Sammakia: There is an attempt to make sense of what the differences are, and that will be part of the roadmap being put together. There will be definitions, and there will be consensus on those definitions by the roadmap group, which is being led by Ravi Mahajan from Intel.

SE: There are currently multiple versions of fan-outs. Which one wins and why?

Butler: There are core fan-outs, which were the original fan-outs. Those are pretty much differentiated. But on the high-density fan-outs there is FOCoS (fan-out chip on substrate) from ASE, InFO (integrated fan-out) from TSMC, SWIFT (Silicon wafer integrated fan-out technology) and SLIM (silicon-less integrated module) from Amkor. From an equipment standpoint it’s very hard to choose which one you’re going to support. That’s the hard thing.

Lakner: We should define these different approaches from the application side to determine what is the best solution. At one time, roadmaps were more or less defined by technology companies. Now it will have to be driven from the application side.

Fig. 2: Fan-in vs. fan-out wafer-level packaging. Source: ASE/SPIL

SE: Can the industry support all of these different options?

Lo: It depends on the application. So for fan-outs there are chip-first and chip-last. But for higher-end applications, the challenge will be to get a finer line/space, no matter which approach you take.

Sammakia: I agree this has to be application-driven. The categories are being driven by the industry, but unless there are applications behind those categories it doesn’t matter. We need to develop standards to define particular approaches. Then different applications can pick what they need.

SE: So let’s take a step back. Regardless of what we call these, there are packages with logic on memory, logic on logic, packageless chips, system-in-package, embedded FPGAs, as well as fan-outs, package-on-package, flip-chip. What’s going to survive here? How many options can the industry support?

Chang: For us, it comes down to scale and economics. All of this integration costs money. Right now, the question is whether the industry will bear that additional cost. It will come down to the best features per dollar.

Lo: Heterogeneous integration is quite important, but everyone has to work together to make all of this work. If you could do everything on a single wafer, then you wouldn’t need all of these different approaches. But if we want to add III-V and II-VI materials, we need new approaches for that—especially for industrial and automotive. So first we need to get the technology, and then all of the IP and integration designs. After that, the economics will follow.

Lakner: We look at this too much from the purely technological side, but what’s changing is that there are now a huge number of small and midsize companies looking for specialized solutions. They want to create new products with a digital footprint. Processor and memory FETs need to come together again, and we need all of the technology vendors to cooperate and really move closer to the customers. Packaging is opening up a whole new world. We have only developed a small percentage of the electronic applications that are possible.

SE: You’re talking about semi-custom or mass customization. Is that feasible?

Butler: If it’s custom and you have boutique shops developing these solutions, how do you make money off of that? The big fabless companies want them to do that and they encourage the packaging companies to go in that direction, but who’s supporting the content? In 2006 and 2007, 3D began getting interesting. A lot of the OSATs put their money into 3D equipment. It’s just now going into production. In the meantime, a lot of other options have come up. Will anyone invest in panel equipment?

Sammakia: The biggest research funding will be for high-end systems. We know that silicon interposer works. 3D works. That’s where the big companies are investing, and those will survive because big companies are driving that.

SE: The whole idea behind advanced packaging going back five years ago was that everything would work like LEGOs, but most implementations have been much more customized. Will it head toward the original concept of snapping pieces together with fewer concerns about power, noise and process node?

Lakner: We have to start on the system side and look for the necessary technologies. Right now there are complex systems being developed for AI in some of these autonomous vehicles, but they use far too much power. That’s not acceptable for cars or robotics. We have to make these things mobile, and bringing down the power is clearly an issue. We have to develop systems that are more or less independent of external power, or which can be autonomous for a certain time period. A roadmap to bring down power consumption will enable a lot of things. We have built FETs that can be utilized for many of these applications. We should increase our emphasis on more photonics and optical applications.

SE: So what’s the big driver here? Is it cost? Performance?

Lo: There are many solutions around performance, but what really matters is cost. You really need to reduce the cost or the only applications that will take advantage of this will be at the very high end. We are working on how to partition designs. Then you can really work on the design and choose the right package, whether it’s 5×5 or something different. If we can do that, we can find the most cost-effective packaging approaches for customers. This is what we’re working on right now.

Chang: Customers are looking for a balance between performance and cost. We have a lot of interesting ideas and solutions that have been proven for a high cost. One of the things we’re trying to drive is economies of scale to bring the cost down. It’s similar to when foundries went from 8-inch to 12-inch. They’re trying to get that scale so that for each process step you get a lot more output. That’s what we’re trying to do with wafer-level fan-out. The reason we’re going to a 600mm panel is for that exact reason. For each process step you get more output. This gives customers assurances that no matter what they design, they can meet the cost that they’re looking for. The features and cost are the key balance points. If you have all the features and it costs too much, nobody’s going to pay for it or put it together. It’s really going to come down to what the market will bear.

Sammakia: If you look at where the research dollars are going, everyone is looking at artificial intelligence and how that’s going to change the world. IBM’s John Kelly (senior vice president of cognitive solutions) sees $2 trillion in final sales. He doesn’t say how much will come down to AI specifically, but AI will be the driver. AI will drive packaging. These packages will be highly integrated analog and digital. It will range from heavy-duty number crunching all the way down to our phones, which will be gathering data. AI is all about number crunching and data acquisitions. So your phone and Fitbit need to be low -power and economical and in high volume. That’s the way the money will flow.

SE: Which is faster and more cost effective, an SoC at 5nm or 3nm or an advanced package?

Lo: Chips will be developed at the most advanced nodes because they require low power and you get benefits from that. But those are very unique applications. If you’re looking at 7nm, that’s a very narrow application area.

Lakner: This has applications in photonics packaging, too. Is it better to put everything on one chip, or do you want to bring in light from the outside? Packaging would help a lot. We can still make a lot of use of platforms in the future, and photonics can add a lot of sensing and imaging. We have 5nm and 3nm in reserve, but there is really not much left after that. With packaging, there is a whole new direction we can work on. I believe the future is in the intelligent package.

Fig. 3: Photonics system integration. Source: Fraunhofer Institute for Applied Optics and Precision Engineering.

Chang: We’re working on silicon photonics now. There is a lot of activity with large data centers and AI because of the bandwidth requirements. Even in the rack itself it’s becoming more an more critical.

Butler: We’ve been dealing with wafer formats. We deposit and etch. So from an equipment standpoint, whether it’s an SoC or SiP, it doesn’t change much. But if SiP involves a fan-out and embedded, then we can get more involved.

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