What’s Next for 2.5D Packaging?

Interposers and bridges, two of the key elements for interconnecting multiple chips and chiplets in an advanced package, are undergoing fundamental changes in how they’re built and assembled.

Interposers are becoming thicker and more complex, while bridges are being used to reduce the assembled cost. Both efforts are facing new challenges.

Interposers are effectively platforms on which multiple components can be assembled — like a micro-sized PCB. The primary material today is silicon, and their sizes, even when built on older process nodes, makes them expensive. They typically handle dense interconnects while passing I/Os, power, and ground to the package substrate below.

Meanwhile, silicon bridges provide dense interconnect between chips or chiplets, embedded in an organic interposer or substrate. Silicon provides the densest interconnect today, so the idea behind bridges is that they can be small and inexpensive, in contrast with silicon interposers. Assembly-yield issues, however, have delayed the cost advantage that bridges eventually promise.

Fig. 1: Interposers vs. bridges. Interposers are large silicon platforms, whereas bridges are small pieces of silicon embedded in an organic interposer or substrate. Source: Bryon Moyer/Semiconductor Engineering

Interposers are getting more layers
AI is driving the complexity of interposers. “We’re now seeing thicker interposers with more metal layers to accommodate the dense routing and high-current paths required for AI and HPC chiplets,” said Aftkhar Aslam, CEO of YieldWerx.

Typical interposers today have up to four layers. A few will see as many as 10 layers, and these thicker interposers will become more common, especially with new generations of HBM memory and wider interfaces.

“After HBM4, we need eight to nine metal layers,” said Pax Wang, director for advanced packages at UMC.

Those extra layers add to the cost, however. “Interposer thickness continues to decrease to enable shorter interconnect paths and better signal integrity,” said Lihong Cao, senior director at ASE Group. “However, there is a balance between the interposer thickness versus mechanical strength and warpage.”

UMC’s Wang agrees. “If we want to increase the thickness of the interposer by adding dielectric layers, that will cause some integration issues,” he said. “For example, no matter whether one uses organic or oxide-based materials, they can cause warpage.”

The challenge with additional layers lies in maintaining planarity. Thicker interposers having more layers want to bow. This is, however, not an insurmountable obstacle.

“As long as the proper thin film stress techniques are implemented, the flatness can be controlled,” said Bassel Haddad, senior vice president and general manager of Skywater Technology’s Florida fab. “But it does get tougher with an increasing number of RDL layers.”

Active interposers emerging
The interposers in use today are overwhelmingly passive. Their role is solely to provide interconnects, and the primary feature is the metal line. Silicon interposers, however, are built from a semiconductor, and their semiconducting properties could be put to use with transistors.

“Active interposers are gaining more adoption, especially for AI/HPC applications when integrating power management, I/O, and optics,” said ASE’s Cao. “It’s mostly limited to high-end and customized solutions due to key challenges in cost, yield, and thermal management.”

That would make the interposer a die as well as an interconnect platform. One must then decide between an interposer process node that supports the desired transistor performance versus building circuits on the already-chosen interposer node. The latter generally will predominate, given the extreme cost of a huge silicon interposer on a leading node.

It turns out Intel may already be doing this. “They have versions of [Foveros] with what you would look at and say is an interposer but is actually an active die,” said Mike Kelly, vice president, chiplets/FCBGA integration at Amkor Technology. “And then you’re putting another functional die on top of that.”

Frequently mentioned as a candidate circuit for an interposer is power management, which involves analog and digital transistors of modest performance. Signal-conditioning circuits and SRAM — especially as cache — are also in researchers’ sights.

But an active silicon interposer is much more expensive than a passive one. Yield now means more than simply having viable metal lines. Transistors must perform well, too. “Active interposers introduce functional test requirements, electrical isolation risks, and die-level repair strategies, extending what was previously a mechanical or parasitic yield problem into an electrical one,” said yieldWerx’s Aslam.

Active interposers require more test
Today’s mainstream interposer flows are insufficient for producing high-quality, reliable active interposers. Rather than simple open/short tests, functional test is now necessary, and those tests may involve both analog and digital circuits.

Electrical isolation also may be necessary between circuits — a consideration not applicable to passive interposers. That complicates a process that today focuses on depositing and patterning oxide and metal. Increasingly, deep-trench capacitors are finding their way, as well, but they’re passive elements helpful in maintaining clean signals. Trenches also may be necessary to keep circuits from interacting.

Because of the high cost of such interposers, it’s critical that they yield well, which is already a challenge for the largest ones. Adding circuits raises the risk that something fails during testing. Die-level repair schemes can help to keep an otherwise failing interposer from being thrown away.

“For OSATs [outsourced assembly and test] and test houses, inspection strategies are also evolving,” noted Aslam. “X-ray and IR imaging are now complemented by electrical continuity and signal-integrity monitoring.”

One step toward an active interposer is the idea of embedding other chiplets in a substrate or interposer, rather than mounting them on top. “With bridge-die technology, designers can integrate PMICs, capacitors, and inductors into the substrate or interposer to make it more energy-efficient,” said Wang.

There is a potential win for active interposers, despite the added costs. “The idea of a smart interposer, so to speak, is probably not going away, but it’s so expensive,” said Kelly. “But once you touch it with a transistor, that interposer wafer is worth a lot more money.”

Photonics can use interposers
Less common are photonic interposers, such as Lightmatter’s Passage, which is essentially a platform on which electrical chips and chiplets can be mounted. The interposer performs electrical-to-optical and optical-to-electrical conversions, making it an active interposer.

“There can be analog circuits,” said Steve Klinger, vice president of product at Lightmatter. “All the control circuitry for stabilizing the various photonic elements are integrated in CMOS inside of Passage. Think of it as an active optical interposer.”

In addition to the conversion components, all the photonics control circuits are built into the interposer, further cementing its active status. The company envisions other analog circuits also having a home there.

An optical interposer can survive with fewer layers than an electrical one because of a critical property of light. “The interesting thing with photonics is that waveguides can cross each other, and that’s okay,” said Klinger.

That can greatly simplify routing, eliminating layers that might have been necessary to facilitate signal crossings.

These interposers may be quite large. Lightmatter is working on ones that are 8X reticle size. This necessitates reticle stitching, something over which the company says it has patents.

Avoiding silicon’s high cost
Much of the activity around 2.5D packaging involves reducing interposer costs. One way of doing that is to find materials that are less expensive than silicon. Organic interposers are less expensive both in materials and fabrication, being built on panels instead of wafers. Process steps such as backside grinding, which silicon requires to expose through-silicon vias (TSVs) aren’t necessary for organic versions.

Organic components such as package substrates typically have metal line and spacing at 10µm, however, which is insufficient for interposer interconnect density. Moving to 5µm lines and spaces requires a cleanroom. Foundries have such cleanrooms, of course, but if OSATs want to build these interposers, a cleanroom means a sizeable investment.

Higher-performance organic interposers are made possible with Ajinomoto build-up film (ABF) which supports higher speeds than the older materials typically found in substrates and PCBs. It’s much more expensive than those older materials, although from a materials standpoint, it’s still cheaper than silicon.

Using organic material to reduce cost is harder when integrating 3D stacks, such as HBM, given increasingly tight pad pitches. Efforts are underway to develop such a capability, but it’s still a research activity.

“I believe at some point silicon interposers and organic interposers will coexist, but they’re going to shift toward organic interposer,” said Skywater’s Haddad. “You’re going see silicon interposers when specific things are needed.”

Glass, which can also be built from panels at a lower cost, is also under consideration. It’s still some years away, however. “There are probably several years to go before glass interposers enter production,” cautioned Wang.

Glass can’t serve for electrically active interposers, but it could host photonic elements. “The advantage is less signal loss, especially for optical signals, and easy light penetration, switching, transformation, and transmission,” said Wang.

The industry still isn’t set up for glass. “Glass needs a big ecosystem play to get all the equipment and standardization set,” said Haddad. “We see them coming in the 2027/2028 timeframe.”

Bridges haven’t yet unlocked lower cost
One of the most promising cost reductions comes from the use of silicon bridges instead of silicon interposers. Each bridge is much smaller, which enables high yield. The cost of a bridge — or several of them — will be far lower than the cost of one interposer made from silicon.

“Embedded silicon bridges provide high-density interconnect and shorter latency at lower cost compared to full interposers,” said Cao.

The idea is to embed the bridges in an organic material — often the package substrate, but also organic interposers. A cavity is created in the organic material. Then the bridge is inserted, aligning it so that the pads on the packages being laid down on the bridges make good contact.

Given that there will always be a package substrate, some may decide that an interposer isn’t necessary. “There are ongoing discussions such as, ‘Why not forget about interposers and just use the ABF substrates or combine it with the DTC [deep-trench capacitors] and bridge dies into the substrate?’” said Wang.

And therein lies the big challenge today — alignment. It’s proven to be quite challenging, and yield is poor. This is what raises the net cost of bridges potentially above that of silicon interposers. It’s not the bridge itself. It’s the poor assembly yield.

Alignment isn’t necessary only for a chip atop a bridge. The chiplets must be aligned across from each other, given straight bridge lines. But offsets are common in such situations, meaning that a straight line patterned in a bridge from one chip to another may miss one or both pads at either end because of the shifted die.

Multibeam says it can repair such offsets. “When you place those bridges, there’s going to be some offsets, and that’s where some of the yield issues come from,” said Ted Prescop, vice president of technology for Multibeam. “We can pattern over that and adapt to the offset.”

This technology can create line/space dimensions measured in nanometers — as few as 30 — rather than the dimensions afforded by standard lithography patterning, measured in microns. The challenge is that each die must be patterned individually, hurting throughput.

Fig. 2: Direct-write electron beam used to correct die-placement offsets. Source: Multibeam

While that might seem like a lot of work, it may beat scrapping the unit. “The alternative is to make the features so large that, even if you have a mechanical offset, you’ve got landing pads that are big enough to encompass that offset,” noted Prescop. “But then you lose a lot of the benefit of the small features.” The added stitching cost may be worthwhile if it fixes a yield issue that’s costing even more.

Silicon remains the go-to for now
For the time being, silicon interposers remain the primary incumbents for 2.5D integration, a process dominated today by a few large players. Organic interposers are gaining steam and will likely take some business from silicon interposers over time, but not all of it. Glass, meanwhile, has yet to reach volume.

As for bridges, their potential remains unfulfilled. Yield is the big problem to be solved. Success there should help reduce the cost of 2.5D integration. If possible, embedding them in substrates rather than an interposer should also bring savings.

Related Reading
Big Changes Ahead For Interposers And Substrates
New materials and processes will help with power distribution and thermal dissipation in advanced packages.
Reticle Stitching Bumps Up Silicon Interposer Costs
Scanner improvements, bridges, and panels may bring relief.
Physics Limits Interposer Line Lengths
Thin lines and limited ground planes keep RDL interconnects short.