Transistor-Level Performance Evaluation Based On Wafer-Level Process Modeling


Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual wafer fabrication software platform and external third-party TCAD software. I’m now happy to report that device-level I-V performance analysis is now a built-in module within the SEMulator3D so... » read more

Advanced 3D Design Technology Co-Optimization For Manufacturability


By Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, and Joseph Ervin Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due to new device structures and the increasing complexity of process innovations introduced to achieve improved product performanc... » read more

Improving Patterning Yield At The 5nm Semiconductor Node


Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconduct... » read more

How To Build A Better MEMS Microphone


We are seeing a lot of interest in simulating noise, particularly for condenser microphones. With any transducer, noise reduction is always a plus, and with microphones there are two specific applications that need low noise. One is where the microphone is positioned away from the sound source, such as in video calling or when using voice commands with tablet computers. The other is where multi... » read more

The Advantages Of FD-SOI Technology


If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where t... » read more

What the Experts Think


Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and ... » read more

The Next 5 Years Of Semiconductor Technology


New, advanced semiconductor processing and architectural technologies take years to perfect and put into production. In the meantime, semiconductor customers continue to demand faster, smaller and higher functioning devices. Semiconductor manufacturers need to decide whether (and when) to jump to the next generation of devices and production technologies, weighing the risk and benefit of bringi... » read more

Reducing BEOL Parasitic Capacitance Using Air Gaps


Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have b... » read more

Using Advanced Statistical Analysis To Improve FinFET Transistor Performance


Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators t... » read more

Silicon Photonics: Solving Process Variation And Manufacturing Challenges


As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur i... » read more

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