Using Dummy Patterning To Solve Etch Uniformity Problems

By James Kim - 21 Nov, 2024 - Comments: 0

Semiconductor devices are made up of hundreds of thin layers of materials stacked by multiple deposition and etch processes. Process engineers need to design the best combination of deposition and etch processes to ensure uniformity across an entire chip area and across the silicon wafer. Uniformity is the most common and critical parameter that is monitored in semiconductor fabrication, especi... » read more

Metal-Oxide-Metal Capacitor Simulation And Modeling By Virtual Fabrication

By Qingpeng Wang - 24 Oct, 2024 - Comments: 0

Metal-Oxide-Metal (MOM) capacitors are passive radio frequency (RF) capacitive devices that are a common component in semiconductor logic chips [1]. A SPICE model of a MOM capacitor is typically used by designers during the design and performance evaluation of logic chip RF circuitry. Traditionally, it may take at least 3 months from the completion of the design layout, wafer fabrication, final... » read more

Reducing Transistor Capacitance At The 5nm Node Using A Source/Drain Contact Recess

By Pradeep Nanja - 19 Sep, 2024 - Comments: 0

In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One potential way to reduce this parasitic capacitance is to add a source/drain contact (CT) recess step when building the source/drain metal structure. However, this additional structure can potentially increase the source/drain to via resistance. Using... » read more

Improving Parasitic Capacitance In Next-Generation DRAM Devices

By Dempsey Deng - 15 Aug, 2024 - Comments: 0

As conventional DRAM devices continue to shrink, increases in parasitic capacitance at smaller dimensions can negatively impact device performance. New DRAM structures may be needed in the future, to lower total capacitance and achieve acceptable device performance. In this study, we compare the parasitic capacitance of a 6F2 honeycomb dynamic random-access memory (DRAM) device to the parasitic... » read more

Improving Line Edge Roughness Using Virtual Fabrication

By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

Virtual Exploration Of Novel Vertical DRAM Architectures

By Taeyon (TY) Oh - 20 Jun, 2024 - Comments: 0

In this article, we demonstrate a pathfinding technique for a novel Vertical DRAM technology. First, we identify important process parameters (defined by current semiconductor production equipment capabilities) that strongly impact yield. By using a virtual model, we then perform experimental optimization of the Vertical DRAM device across specific target ranges, to help predict and improve the... » read more

Understanding CFETs, A Next Generation Transistor Architecture

By Sam Sarkar - 23 May, 2024 - Comments: 0

Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

Exploring Process Scenarios To Improve DRAM Device Performance

By Yu De Chen - 18 Apr, 2024 - Comments: 0

In the world of advanced semiconductor fabrication, creating precise device profiles (edge shapes) is an important step in achieving targeted on-chip electrical performance. For example, saddle fin profiles in a DRAM memory device must be precisely fabricated during process development in order to avoid memory performance issues. Saddle fins were introduced in DRAM devices to increase channel l... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors

By James Kim - 22 Feb, 2024 - Comments: 0

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications

By Brett Lowe - 18 Jan, 2024 - Comments: 0

In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of ... » read more

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