category: Perfecting The Process

category: IoT, Security & Automotive

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes
By Dempsey Deng - 16 Mar, 2023 - Comments: 0

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

The Other Side Of The Wafer: The Latest Developments In Backside Power Delivery
By Sandy Wen - 16 Feb, 2023 - Comments: 0

At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew off a robot blade during a wafer transfer. After cleaning up the mess, we remembered that a variety of thin films could be deposited on the wafer backside, which could decrease its friction coefficient. Slowing down the wa... » read more

Automotive MEMS Accelerometer Design Verification: A Real Life Example
By Arnaud Parent - 15 Dec, 2022 - Comments: 0

Standard Finite Element (FE) models, especially those that incorporate multiple physical domains, consist of detailed representations of a device that include a large number of Degrees of Freedom (DoF). The Degrees of Freedom in a design are the number of independent variables or parameters needed to describe the motion or state of the device. Generally, the larger the number of Degrees of Free... » read more

Creating Airgaps To Reduce Parasitic Capacitance In FEOL
By Sumant Sarkar - 17 Nov, 2022 - Comments: 0

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the effective dielectric constant of the material layers between the gate and source/drain. This can be done by creating airgaps in the dielectric material at that location. This type of work has been do... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

3D NAND Virtual Process Troubleshooting And Investigation
By Brett Lowe - 18 Aug, 2022 - Comments: 0

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form of unanticipated negative interactions between upstream and downstream process modules. These barriers can create a long delay in the development cycle and increase costs. ... » read more

Quantum Computers And CMOS Semiconductors: A Review And Future Predictions
By Michael Hargrove - 16 Jun, 2022 - Comments: 0

With the advent of quantum computing, the need for peripheral fault-tolerant logic control circuitry has reached new heights. In classical computation, the unit of information is a “1” or “0”. In quantum computers, the unit of information is a qubit which can be characterized as a “0”, “1”, or a superposition of both values (known as a “superimposed state”). The control c... » read more

There Is Plenty Of Room At The Top: Imagining Miniaturized Electro-Mechanical Switches In Low-Power Computing Applications
By Gerold Schröpfer - 19 May, 2022 - Comments: 0

The first computers were built using electro-mechanical components, unlike today’s modern electronic systems. Alan Turing’s cryptanalysis multiplier and Konrad Zuse’s Z2 were invented and built in the first half of the 20th century, and were among the first computers ever constructed. Electro-mechanical switches and relays performed logic operations in these machines. Even after computers... » read more

BEOL Integration For The 1.5nm Node And Beyond
By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

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