category: Manufacturing, Packaging and Materials

category: Auto, Security & Edge AI

Why Metal TIM Warpage Simulations Fail—And How To Fix Them
By Dambi Jo - 16 Jul, 2026 - Comments: 0

By Dambi Jo, JiHyun Kim, GaHyeon Kim, TaeKyeong Hwang, WonChul Do, and KyungRok Park In the semiconductor packaging industry, it is common practice to predict warpage and stress levels through simulation prior to actual product fabrication. This approach helps minimize the cost and time associated with prototype production [1]. The need for simulation-driven design and material optimization ... » read more

From Feature-Scale Simulation To Digital Twins: Helping Process Engineers Tackle Growing Complexity
By Saurabh Suryavanshi - 16 Jul, 2026 - Comments: 0

For process engineers facing rising manufacturing complexity, physics-based simulation provides the foundation for understanding what is happening on the wafer. AI, automation, and digital twins become powerful only when they build on that foundation, enabling faster exploration without losing trust, calibration, or engineering judgment. The growing challenge of semiconductor manufacturing Se... » read more

Can Fine-Pitch Hybrid Bonding Go High Volume?
By Gregory Haley - 16 Jul, 2026 - Comments: 0

Key Takeaways: Fine-pitch hybrid bonding extends a proven production technology into a manufacturing regime with much smaller margins for particles, surface variation, distortion, and placement error. Die-to-wafer integration allows known-good-die selection, but it exchanges wafer-level parallelism for repeated handling, alignment, and bonding operations. Reaching high volume will de... » read more

Optimizing The Nano-TSV-to-BPR Connection In Backside Power Networks
By Assawer Soussou - 16 Jul, 2026 - Comments: 0

As technology nodes continue to scale, maintaining power and performance while reducing the footprint has become increasingly challenging. Backside power delivery networks (BSPDNs) address this challenge by moving the power delivery network to the wafer backside. What is backside power delivery (BSPDN)? The problem being solved by BSPDNs is similar to getting people out of a crowded offic... » read more

New Nonvolatile Memory Winners Emerge
By Bryon Moyer - 16 Jul, 2026 - Comments: 0

Key Takeaways:  MRAM and RRAM will likely coexist, each with a different focus. PCRAM isn’t being ported onto finFET nodes. FeRAM is seeing new life, while a newcomer has a new NVM bit cell. Newer nonvolatile memory (NVM) technologies are poised to take over from flash in embedded applications on newer process nodes. Magnetic RAM (MRAM) and resistive RAM (RRAM) appear to ... » read more

Co-Packaged Optics for Multi-Die Designs
By Synopsys - 16 Jul, 2026 - Comments: 0

As bandwidth scales to 800G and 1.6T, electrical interconnects and pluggable optics reach limits in power, distance, and signal integrity. Co‑packaged optics (CPO) addresses these challenges by moving optical interconnect closer to silicon, reducing electrical path length, lowering power per bit, and enabling higher bandwidth density. This white paper explains why CPO is emerging now, how it ... » read more

Alternative Materials For Hybrid Bonding
By Katherine Derbyshire - 16 Jul, 2026 - Comments: 0

Key Takeaways:  Hybrid bonding is essential for the interconnect density that high-bandwidth workloads require. Successful implementation depends on control of surface chemistry and surface topography — clean surfaces with topography that can accommodate expansion during bonding. To improve interface quality and manage stresses related to thermal expansion mismatch, manufacturers ... » read more

Accelerating Sustainability With Smart Manufacturing
By Mark da Silva - 16 Jul, 2026 - Comments: 0

By Brian J. Coppa, Amit Srivastava, Mark da Silva, and Anshu Bahadur The SEMI Smart Manufacturing Initiative is a global effort focused on leveraging the most advanced technology to enhance productivity of electronics manufacturing facilities. Among the key technology advances this group seeks to promote is the value of implementing Industry 4.0/5.0 technology to deliver increased return-o... » read more

Creating A Moore’s Law For AI Scaling
By Laura Peters - 24 Jun, 2026 - Comments: 0

Key Takeaways: AI scalability will require full-stack co-optimization, not just bigger data centers. AI workloads require a 10X compute efficiency gain over 10 years, making collaboration across algorithms, architectures, devices, packaging, and communication fabrics essential to deliver a 10X improvement in compute efficiency over the next decade.  Edge AI chips are moving to leadi... » read more

Mask Economics Shape High-NA EUV Adoption
By Gregory Haley - 22 Jun, 2026 - Comments: 1

Key Takeaways: Mask costs are not stopping leading-edge scaling, but they increasingly influence design, node, and process choices. High-NA EUV will tighten requirements for CD, EPE, local CDU, mask 3D modeling, stitching, and materials. Reduced depth of focus in High-NA EUV will drive new resist, etch, film, and absorber approaches. Experts at the table: Semiconductor Engin... » read more

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