Enabling Production-Ready AI For Semiconductor Manufacturing


Semiconductor inspection has always been a scalability problem. Inspection teams are buried in manual reviews because the machines on the line throw false rejects, miss real defects, and can't learn from the data they're already producing. The job hasn't really changed in decades. Find defects faster. Find them with higher sensitivity. Keep cost down. And whatever you do, don't bury the review ... » read more

Cost-Effective High-Performance Flip Chip MicroLeadFrame (fcMLF) Package Introduction


Abstract "The demand for cost-effective leadframe packages continues to grow, particularly for automotive and commercial applications. These designs require smaller form factors, enhanced thermal and electrical performance, and proven reliability. Flip chip on leadframe technology offers significant advantages over traditional wire-bonded MicroLeadFrame (MLF) and high-cost laminate Flip Chip... » read more

Mask Technology Faces A New Set Of Challenges


Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

When Semiconductor Materials Misbehave


Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

TSV Complexity Leads To Manufacturing Bottleneck


Key Takeaways: Through-silicon vias are the biggest enabler of 3D chip stacking and chip-to-PCB connections through silicon interposers. The AI boom is causing HBM and advanced assembly shortages, straining the supply chain. Optimization around etch, fill and reveal help reduce TSV cost. Through-silicon vias (TSVs) provide essential interconnects between DRAM dies inside hig... » read more

Panel-Level Packaging’s Second Wave Meets Engineering Reality


Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Chiplet Standards Aim For Plug-n-Play


Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

Silicon Photonics Lights The Way To More Efficient Data Centers


Key Takeaways Photonic interconnects potentially increase bandwidth density while significantly reducing power consumption. AI workloads are driving their adoption in data centers. On the other hand, photonic interconnects require a variety of different materials, introducing process compatibility and thermal and mechanical stress issues. Integrated electro-optical I/O modules are th... » read more

eBeam Initiative At SPIE ALP 2026: Continuing Progress On Curvilinear, EUV, And Data Challenges


The eBeam Initiative’s annual lunch at SPIE Advanced Lithography and Patterning has long served as a focal point for eBeam technology education for the industry. This year marked our 17th gathering, with approximately 150 attendees joining us. As in past years, the value of the session was less about any single topic and more about the collective signal across different parts of the ecosystem... » read more

Breakthrough Thin GaN Chiplet Technology


Researchers at Intel Foundry have demonstrated a gallium nitride (GaN) chiplet technology built on 300 mm GaN-on-silicon wafers, marking a significant leap forward in semiconductor design. Presented at the 2025 IEEE International Electron Devices Meeting (IEDM), this work tackles one of the most pressing challenges in modern computing: how to deliver more power, speed, and efficiency in an incr... » read more

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