GaN Power Devices Go Vertical


Key Takeaways: On paper, GaN is an excellent candidate for high-voltage power applications. That potential has been difficult to realize due to the lack of sufficiently high-quality starting material. In particular, high-voltage applications require vertical designs. Recent advances in GaN growth are making these designs more feasible. Promising designs and complete process flows hav... » read more

Making On-Chip Photonics Manufacturable


Key Takeaways: System-level energy and bandwidth pressures are pulling optics into the package faster than the manufacturing flow can mature. Photonics combines front-end fabrication, materials, thermal, cleanliness, and test into one problem that can’t be solved domain by domain. Test is moving upstream because discovering an optical failure after final assembly forfeits every goo... » read more

Packaging Technologies Redefine AI And HPC Scalability Limits At ECTC 2026


The 2026 IEEE Electronic Components and Technology Conference (ECTC) showcased how advanced packaging can redefine the scalability limits of artificial intelligence (AI) and high-performance computing (HPC). Across 20 technical papers, Intel Foundry engineers and collaborators highlighted breakthrough innovations — from Embedded Multi-die Interconnect Bridge-T (EMIB-T) enabling large multi-d... » read more

GaN Power Devices Power Up


Key Takeaways: GaN devices are gaining traction due to their ability to tolerate higher voltages. New approaches such as chiplets offer faster switching with less loss. The first applications to benefit from GaN will be low-voltage consumer devices; industrial applications require more work. As electrical power displaces fossil fuels in more applications, system designers ne... » read more

The Sub-2nm Paradox


Key Takeaways: Process variation and physics are changing semiconductor design, manufacturing, and economics at 2nm and below. Even though new manufacturing processes are being introduced, it's taking longer for them to mature. The focus for many chip designs is faster data movement and more efficient computing, rather than just relying on more transistors per mm2. At 2nm an... » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology


Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table... » read more

Beyond Ideal Crystals: The Case For Scale In Atomistic Modeling


Almost all computer simulations face the same trade-off: larger models can be more realistic and therefore more useful, but they also take longer to run. Engineers and scientists are therefore faced with an almost daily challenge of choosing a model that is detailed enough to capture the important details without making the calculation impractically expensive. "All models are wrong, but some... » read more

Process Variation In The Era Of Scaling: Improving Uniformity With Dummy Fill


As semiconductor patterning continues to scale, even small layout nonuniformities can lead to noticeably different process outcomes. Real chip layouts contain a mix of dense regions, large open regions, and isolated features. As a result, the etch process encounters different “local environments” across the wafer. Even with the same process settings (or recipe), some areas may etch mo... » read more

With Chiplets, What Role Does Economics Play?


Key Takeaways: For the data center, chiplet economics matter, but they’re not a primary decision-driver. With the exception of processor families, chiplets cannot address consumer markets today, where economics dominate. If a chiplet marketplace materializes, the economics may be friendlier because chiplets will have multiple customers and applications. Chiplets are notori... » read more

Advancing Heterogeneous Integration Through Industry Roadmap Improvements


Heterogeneous integration requires comprehensive roadmaps to support collaboration across the design and manufacturing of the next generation of semiconductor products and the systems they support. A global team of researchers from a broad spectrum of industry, academia, and research institutes led by Intel has published a perspective in the March 2026 issue of Nature Reviews Electrical Enginee... » read more

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