Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication


By Swapnil Kailash More and Roopa Hegde As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advan... » read more

Meeting High-Frequency And Power Density Challenges With Flip Chip MLF Packaging


The relentless march of semiconductor scaling continues to reshape the packaging landscape, driven by Moore’s Law and the demand for higher performance in increasingly compact form factors [1]. Over the past two decades transistor density has increased exponentially, with leading-edge processes now achieving densities exceeding 100 million transistors per square millimeter. Certain applica... » read more

Automate And Speed Up TCAD Calibration With Expert Modules And ML Calibration Accelerator


Increasing complexity in semiconductor manufacturing has pushed the time to market and R&D costs significantly higher. In the world of AI, there is increased focus on efficiency to help address these issues simultaneously. Wafer-based learning, which is an iterative and linear process, is a key contributor to the increased semiconductor development time and cost. Technology computer-aided d... » read more

Advancing Autonomous Fabs


The semiconductor industry is entering a critical transition phase toward Autonomous Semiconductor Fabs, driven by escalating process complexity, increasing equipment costs, and heightened demands for operational stability. In this environment, preventive maintenance (PM) is no longer a peripheral operational function but a central determinant of equipment availability, productivity, and manufa... » read more

The Thermal And Power Realities Of The AI Era


The rapid growth of AI has created a surge in the global energy consumption at a rate never seen before. Today, data centers account for approximately 415 terawatt-hours (TWh) of electricity globally. To put this into perspective, the annual energy consumption of the United Kingdom in 2023 measured at 309 TWh. The International Energy Agency (IEA) projects data centers’ energy consumption wil... » read more

Challenges In Scaling Chips To 2nm And Below


Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Beating The Heat In 3D Packages


Key Takeaways: Thermal management is a central design constraint, requiring early, thorough planning. Accurate thermal simulation requires AI-driven adaptive meshing and real-world validation. Innovative STCO strategies can drastically reduce GPU peak temperature. As HPC and AI accelerators push power densities to 1kW and beyond, the heat generated by rapidly switching tran... » read more

Quantifying The Impact Of Gravity On Strip Warpage Across Assembly Stages


The mechanical behavior of electronic packages is an important consideration at each stage of the assembly process. Many packages are assembled in strip format, making strip warpage a critical challenge for manufacturability and yield. Accurate simulations for strip warpage are an effective tool to determine what factors cause large warpages and to explore solutions before assembly. In these si... » read more

Exploring The Frontiers Of Lithography And Patterning: Highlights From SPIE Advanced Lithography + Patterning 2026


Leading‑edge system-on-chip (SoC) designs at deep submicron nodes are stretching lithography and patterning capabilities across the entire manufacturing flow. Extreme ultraviolet (EUV) lithography has become central to printing advanced features, using high‑power pulsed lasers to generate a plasma light source and reflective optics to project mask patterns onto the wafer. As error budgets t... » read more

Process Model Precision: Calibrating For Accurate Predictions Of FinFET Device Profiles


In modern semiconductor process integration, rapid and well-informed path finding is essential for on-time product release. Virtual Design of Engineering (DOE) and predictive modeling can expose integration risks early; however, their value depends on accurate process models calibrated to real fab behavior.1 Reliable prediction requires strong correlations between model inputs and measurable... » read more

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