Advanced Packaging Moving At Breakneck Pace


Experts at the Table: Semiconductor Engineering sat down to discuss advances in packaging with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. L-R: Synopsys' Roosendaal; ASE's Che... » read more

Assembly Design Rules Slowly Emerge


Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Electrifying Everything: Power Moves Toward ICs


As electronic systems grow increasingly complex and energy-intensive, traditional power management methods — centered on centralized systems and external components — are proving inadequate. The next wave of innovation is to bring power control closer to the action — directly on the chip or into a heterogeneous package. This change is driven by a relentless pursuit of efficiency, scala... » read more

Upcoming Challenges And Changes In Semiconductor Materials


Semiconductor Engineering sat down with Dan Brewer and Srikanth Kommu, co-CEOs at Brewer Science, to talk about current and future changes in materials used in semiconductor manufacturing and adjacent markets. What follows are excerpts of that conversation. SE: What was behind the decision to have co-CEOs instead of just one? Brewer: We see a lot of value to having multiple perspectives b... » read more

Improving GaN Device Architectures


As the universe of applications for power devices grows, designers are finding that no single semiconductor can cover the full range of voltage and current requirements. Instead, combination circuits use different materials for different parts of the overall operating range. GaN is especially well-established in low-power applications like chargers for personal electronics, while silicon and... » read more

What’s Next For Through-Silicon Vias


From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Baby Steps Toward 3D DRAM


Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive. Severa... » read more

Navigating Increased Complexity In Advanced Packaging


As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Challenges In Powering Electrification With GaN And SiC


The wish list of device properties that designers of power management systems would like to have is lengthy, but no single material is yet sufficient for the full range of power control applications. For control transistors to handle power surges, breakdown voltages should be at least triple the expected operating voltage — 1.2 kilovolts or more for many electric vehicle applications, and ... » read more

NAND Flash Targets 1,000 Layers


The chip industry is pushing to quadruple the stack height of 3D NAND flash from 200 layers to 800 layers or more over the next few years, using the additional capacity will help to feed the unending need for more memory of all types. Those additional layers will add new reliability issues a number of incremental reliability challenges, but the NAND flash industry has been steadily increasin... » read more

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