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Geo-Spatial Outlier Detection


Comparing die test results with other die on a wafer helps identify outliers, but combining that data with the exact location of an outlier offers a much deeper understanding of what can go wrong and why. The main idea in outlier detection is to find something in or on a die that is different from all the other dies on a wafer. Doing this in the context of a die’s neighbor has become easie... » read more

Automotive Innovations In Semiconductors


By Jeff Barnum, Janay Camp, and Cathy Perry Sullivan The semiconductor industry performed better than expected in 2020 despite the impact of COVID-19 on the global economy and is preparing for accelerated growth in 2021 and beyond. The global coronavirus pandemic significantly increased demand for communications electronics and fueled the growth in cloud computing to support remote work and ... » read more

Design For Test Data


As design pushes deeper into data-driven architectures, so does test. Geir Eide, director for product management of DFT and Tessent Silicon Lifecycle Solutions at Siemens Digital Industries Software, talks with Semiconductor Engineering about a subtle but significant shift for designing testability into chips so that test data can be used at multiple stages during a device’s lifetime. » read more

Streaming Scan Network


The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. In the traditional approach to delivering scan test data to cores, each core requires a dedicated connection to chip-level pins, which doesn’t allow for much flexibility, as the dependencies betwee... » read more

5G Chips Add Test Challenges


The advent of chips supporting millimeter-wave (mmWave) 5G signals is creating a new set of design and testing challenges. Effects that could be ignored at lower frequencies are now important. Performing high-volume test of RF chips will require much more from automated test equipment (ATE) than is required for chips operating below 6 GHz. “MmWave design is a pretty old thing,” said Y... » read more

Packetized Scan Test Delivery


The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To address these challenges, we now have the option of implementing a packetized data network for scan test that moves the scan data through the SoC much more efficiently than the traditional pin-... » read more

Achieving CDC Signoff On Multi Billion Gate Designs With Hierarchical CDC Flow


For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many complex IPs operating at different clock frequencies, which can stress the verification cycle. Generally, design and verification teams are spending an increasing amount of time to ensure that the SoC ... » read more

Cleaning Up During IC Test


Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

What Does It Take To Build A Successful Multi-Chip Module Factory?


When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t ex... » read more

Development Of High Voltage General-Purpose Pin-Electronics


Currently, there is a demand in Automated Test Equipment (ATE) to test both high-speed/low-voltage amplitude devices manufactured in advanced processes and low-speed / high-voltage amplitude devices manufactured in legacy processes by a pin-electronics equipment. However, it is difficult to achieve both the operating speed over than 1Gbps and the wide I/O range over than 10Vpp, due to the trade... » read more

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