Test Is Becoming A Horizontal Process


Semiconductor test, once a discrete part of a well-orchestrated series of manufacturing steps, is looking more like a process that extends from the early concept stage in design to the end of life of whatever system that chip ultimately is used for. This has important ramifications for safety-critical markets in general, and the semiconductor industry in particular. Both worlds have been inc... » read more

MRAM Process Development And Production Briefing


By Dr. Meng Zhu, Dr. Roman Sappey, and Jeff Barnum MRAM (Magnetoresistive Random-Access Memory) is a type of non-volatile memory (NVM) that utilizes magnetic states to store information. The basic structure of MRAM is a magnetic-tunnel junction (MTJ), which consists of two ferromagnetic (FM) layers separated by an insulating tunnel barrier (Fig.1). When the magnetizations of the two magnetic... » read more

Test Costs Spiking


The cost of test is rising as a percentage of manufacturing costs, fueled by concerns about reliability of advanced-node designs in cars and data centers, as well as extended lifetimes for chips in those and other markets. For decades, test was limited to a flat 2% of total manufacturing cost, a formula developed prior to the turn of the Millennium after chipmakers and foundries saw the traj... » read more

Improving Functional Safety For ICs


The exponential growth of electronics in automobiles have stimulated significant innovation towards the development of advanced safety mechanisms. In addition to very high-quality manufacturing test, ICs for safety-critical applications need in-system test to detect faults and monitor circuit aging. Scan-based logic built-in-self-test (LBIST) is the technique used for in-system test, but tradit... » read more

Taming Novel NVM Non-Determinism


New memory technologies may have non-deterministic characteristics that add calibration to the test burden — and may require recalibration during their lifetime. Many of these memories are in development as a result of the search for a storage-class memory (SCM) technology that can bridge the gap between larger, slower memories like flash and faster DRAM memory. There are several approache... » read more

What’s WAT? Testing At The End Of Manufacturing


The high costs of building, resourcing and operating a foundry fabricating integrated circuits are well known. Fabless companies avoid this capital cost and focus on design and innovation in their area of expertise. On the other hand, the fabless company relies on the expertise and skills of the foundry to produce quality wafers. Many times a process used by a fabless company to manufacture... » read more

Manufacturing Optimization With Digital Thread


Data is everywhere, and if you know what to do with it, can be tremendously valuable. Huge volumes of data are collected in manufacturing industries across the supply chain, with the help of technologies such as IoT platforms, sensors, and edge devices. However, data is only as good as the value extracted from it, and getting the most out of data is challenging. Because information is often con... » read more

Grading Chips For Longer Lifetimes


Figuring out how to grade chips is becoming much more difficult as these chips are used in applications where they are supposed to last for decades rather than just a couple of years. During manufacturing, semiconductors typically are run through a battery of tests involving performance and power, and then priced accordingly. But that is no longer a straightforward process for several reason... » read more

Wafer Test Challenges For Chiplets


In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage. From a test perspective, making chiplets a mainstream technology depends on ensuring Good Enough Die at a reasonable test cost. Wafer-level test plays a critical and intricate role in the chipl... » read more

AI Chip DFT Techniques For Aggressive Time-To-Market


AI chips have aggressive time-to-market goals. Designers can shave significant time off of DFT and silicon bring up using the techniques described in this paper. Leading AI semiconductor companies have already had success with Tessent DFT tools. To read more, click here. » read more

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