New Methodologies Create New Opportunities

By Brian Bailey - 27 Apr, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardwa... » read more

Automation And Fault Simulation Of Safety-Critical FPGA Designs

By Joe Mallett - 15 Dec, 2020 - Comments: 0

Functional safety is a major challenge for field programmable gate arrays (FPGAs) and other semiconductor designs. Safety requirements go beyond traditional verification, which focuses on design bugs. Chips in safety-critical applications must be able to handle a variety of faults from sources such as temperature and power extremes, device aging, radiation, ionization and component failures. Ap... » read more

Chinese EDA

By Brian Bailey - 29 Oct, 2020 - Comments: 0

If you saw this headline and thought you missed a press release, don't panic. China has not, at this point, announced to the world that it has a suite of EDA tools ready to roll. The rest of the world is content to look at the substandard attempts it have made so far and write them off as not being capable of developing competitive EDA software. But in all likelihood, given the current politica... » read more

Verification Of Multi-Cycle Paths And False Paths

By Joe Mallett - 24 Sep, 2020 - Comments: 1

All chip designers know that they must take special care to avoid metastability problems when they have multiple, asynchronous clock domains. In contrast, a design in which all clocks are synchronous may appear simple. Logic synthesis ensures that the shortest paths between registers don’t have races and that the longest paths fit within the target cycle time. However, single-clock design is ... » read more

Logic Synthesis Basics For FPGA

By Sunil Sahoo - 27 Aug, 2020 - Comments: 0

In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college. It was time consuming and very error prone. This works fine for designs with a few hundred gates, but as the designs get larger and larger this became non-feasible. Design... » read more

When Verification Leads

By Brian Bailey - 25 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, CEO for VTool; Adnan Hamid, CEO for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom... » read more

Enabling Cheaper Design

By Brian Bailey - 13 Sep, 2018 - Comments: 1

While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs are traditionally built using standard parts, such as microcontrollers, but as additional... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer