High-Speed Manufacturing And In-Field Scan Test Access Via PCI Express For GPIO Limited SoCs

By Ash Patel and Shubharthi Datta, Synopsys, and Chuanyun Fan, Cisco

Today’s huge, deep submicron system on chip (SoC) designs present many challenges at every stage of development, from architectural exploration to volume production. This post addresses the specific hurdle of effective and efficient manufacturing tests for these complex devices. It outlines a commercially available solution and reports the results from a recent project at Cisco. These results were presented in a talk at the SNUG Silicon Valley 2026 event; this post makes the case study available to a wider audience.

The root of the test challenge is the ever-widening ratio between silicon capacity and available pin count. Chips have scaled dramatically in capacity as geometries have shrunk, but the physical parameters associated with off-chip IO connections have not kept pace. The traditional approach of using slow GPIO pins for test access no longer suffices. It is impractical to add many GPIO pins to increase bandwidth and test the huge amount of functionality within large SoC devices.

The preferred solution is to reuse existing functional high-speed IO pins for test access. The latest generations of USB and PCI Express (PCIe) can transfer high volumes of data quickly, greatly reducing time spent on automated test equipment (ATE) during chip manufacturing. In-system structural test access provides the necessary bandwidth without the addition of multiple GPIO pins.  Reuse of functional pins also opens the possibility of running chip tests during in-field deployment to check for degradation and aging as part of an effective silicon lifecycle management (SLM) strategy.

This chip project at Cisco included PCIe Gen4 as the primary interface for functional (mission mode) operation. PCIe Gen4 supports up to 16 GT/s per lane (with 4 lanes of Gen4 used in this Cisco design, it can achieve up to 64 GT/s data rate), allowing gigabit-level data rates for scan, test access port (TAP), and functional monitor data. Cisco selected the Synopsys SLM High-Speed Access & Test (HSAT) IP as the link between the PCIe port and the internal scan-based test architecture. The diagram below shows how this IP is used to support manufacturing test with ATE.

The team found that there was significant clock skew across the flip-flops in the scan chain, and they added a “re-timer” FIFO to absorb the skew and reduce the number of scan clocks to be propagated to the full design. HSAT connects to the PCIe Gen4 interface via an Arm AXI fabric, a widely used industry-standard bus. The connection between the PCIe interface and the ATE is provided by an Advantest’s Link Scale digital channel card, which supports high-speed transfer for both software-based functional test and scan-based test.

Given the long fabrication time and high cost for producing chips, pre-silicon verification of all design functionality is essential before tape-out. This includes simulation of scan test operation. The Cisco team used Synopsys TestMAX for automatic test pattern generation (ATPG) at the block level and TestMax ALE to convert these patterns to a chip level Standard Test Interface Language (STIL) file that could run on the ATE. The team performed three levels of simulation:

1. Standalone block level simulation with the generated ATPG patterns
2. VIP + PCIe + DMA + HSAT loopback patterns, including performance test – upper figure below
3. ALE test patterns + full scan netlist – lower figure below

After successful simulation and tape-out, the team prepared for the arrival of silicon. This included setting up the Advantest Link Scale hardware and software, designing the ATE board and probe, preparing and compressing the test data as a PCI payload in TDAT format, and setting up for diagnosis of any test failures. Silicon bring-up included the following steps:

• PCIe PHY link up
  • STIL patterns
  • JTAG register programming + GPIO sequence (including chip initialization)
• PCIe enumeration
  • Driven by Link Scale after PHY link up
  • Used HSAT loopback patterns to validate PCIe transactions
• ATPG setup/configuration JTAG patterns
  • STIL patterns or TDAT for HSAT driving JTAG
• ATPG scan/capture payload
  • TDAT format
  • No obvious switching overhead between STIL (tester) and TDAT (Link Scale host)
• Shmoo
  • Kept PCIe VDD separate and constant
  • Goal was to check ATPG results

In summary, the Cisco engineers were able to successfully perform simulation-based verification of scan test operation in pre-silicon mode. When chips arrived, bring-up was fast and efficient. They were able to meet their primary goal of achieving full PCIe Gen4 speed during production test of both wafers and packaged parts. They commented that their future plans include testing scan operation between simulation and silicon using Synopsys HAPS (Hardware-Assisted Prototyping System) and the Synopsys ZeBu EP scalable unified hardware platform for emulation.

The Cisco team concluded that their approach was an effective way to replace GPIO-based test access, enabling faster, more scalable, and lifecycle-wide testing while conserving limited pins. To learn more about high-speed test access and its role in scalable manufacturing and in-field testing, explore Synopsys SLM HSAT IP.

Shubharthi Datta is senior director of solutions engineering at Synopsys.

Chuanyun Fan is director of hardware engineering at Cisco.