Variation In Low-Power FinFET Designs

Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.


One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield.

While variation is generally well understood, there are more sources of variation at each new node and the effects are additive. Moreover, traditional solutions to this problem no longer work, and rising complexity makes it more difficult to model. As a result, chipmakers are being forced to look for alternative approaches than just guard-banding.

“There is a lot more variation with the smaller finFET process geometries, especially at 10nm and below, due to the shrinking node process and wire alignment of the various lithographic effects,” said Mary Ann White, director of product marketing for automotive, low power and finFET implementation at Synopsys. “At ultra-low voltages the variation is more magnified, where waveform distortion also happens due to increased wire resistance and Miller effects (higher capacitance),”

Indeed, every new node using the latest FinFET technologies introduces additional challenges when it comes to manufacturing yields, Jerry Zhao, product management director at Cadence, pointed out. “From a power and signal integrity perspective, electromigration (EM) and its association with thermal consumption such as self-heating-effects (SHE) introduces design challenges with the chip’s reliability analysis. For example, statistical EM budgeting (SEB) or failure-in-time (FIT) calculations are becoming mainstream design requirements for automotive chip designs.”
For example, an ultra-low voltage supply such as Vdd=650mV at 5nm FinFET node makes IR-drop and EM signoff much harder to complete than Vdd=950mV at 16nm FinFET node, Zhao said. “Traditional guard-banding like 10% Vdd leaves only a 65mV design margin with a 30% drop between the two nodes. Considering a near 10X increase on wire’s resistance, the same amount of current will induce a much higher voltage drop on the 5nm node and make it very difficult to meet the above 10% threshold.”

The graph illustrates that the resistance value has increased rapidly, by 10X, when moving from 16nm FinFET down to 5nm FinFET. The larger the metal wire’s resistance, the bigger the IR drop will be with the same current flow. In other words, IR drop has become a more significant design issue at 5nm than 16nm.
Source: Cadence

And even if a design has met this traditional methodology of “guard-banding” in electrical signoff, failing at 7nm FinFET silicon has proven that a new technology in the combination of IR-aware static timing analysis (STA) from EDA vendors is required, he noted. “At a given voltage variation level, a cell’s delay jumps much higher at 5nm; with more sensitive delta-T/delta-V behaviors. This IR-drop sensitivity is on a ‘good’ path, per the guard-banding standard, and is likely to be a ‘failed’ path in silicon because of the accumulative impact of individual cell’s voltage drops. Identifying and analyzing such IR-drop sensitive paths, however, is not easier than finding a needle in the haystack and requires the latest machine learning technology and a unified timing + power electrical signoff engine.”

Accounting for these effects is a growing problem for a variety of chips developed at advanced nodes, including those developed for AI, machine learning, both within data centers and at the edge. For edge devices this is particularly problematic, because the amount of data that needs to be processed is increasing far faster than improvements in battery technology will allow.

Increasing transistor density by moving to the next nodes helps keep pace with the rise in data, and lowering the voltage minimizes the impact on battery life. But increased density also means that tolerances for noise, power and layout are much tighter than at older nodes. Any type of variation can disrupt this finely tuned balance—even printing something that is off by a few nanometers because one EUV scanner is different from another.

“Getting alignment within a nanometer or two is super-critical, because that actually determines the resistance path to the transistor,” said Klaus Schuegraf, vice president of new products and solutions at PDF Solutions. “Variation matters here because the Vdd is lower. You’re talking about 0.75V for Vdd. So while 100mV of variation was okay in the past, now 10mV or 15mV will cause a problem.”

Mitigating the effects
Process variation typically has been addressed by adding extra margin into designs. But at advanced nodes, extra circuitry can have a significant impact on both performance and power. With ultra-low voltage designs, tolerances for things like noise are tighter. So while variation might cause minor issues at 28nm, it can render a chip unusable at 7nm. It also can affect the reliability of a chip over its projected lifetime.

“Models for reliability need to include process variation,” said Andre Lange, group manager for quality and reliability at Fraunhofer EAS. “In the past, you looked at the corner cases, added margin, and then it was considered safe. That will not work any more at new technology nodes or even at older nodes for industrial applications that are used 24 x 7. We’re seeing different points of view on margin because of transistor degradation. So you have pessimistic models and accurate models, where there is no extra margin, and you see how much you really need.”

Variation is a complicating factor from design through manufacturing, and a number of techniques have been developed to mitigate these effects. Optimization and analysis based on parametric on-chip variation (POCV) from synthesis through place and route and sign-off can help. So can technologies like advanced waveform propagation (AWP) to model the waveform distortion of the advanced nodes and perform timing-driven optimization.

But variation also is a key driver for utilizing techniques such as adaptive voltage scaling (AVS) and dynamic voltage and frequency scaling (DVFS). While these approaches have been around for some time, they have seen limited adoption because they were more difficult to implement than adding margin. Now these techniques are becoming more widespread as a way of saving power.

“Increased process variability of advanced node CMOS technologies has become a significant factor to the development of SoC devices when designing for speed and power performance,” said Ramsay Allen, vice president of marketing at Moortec Semiconductor. “Self-determination of device temperature, supply voltage levels, and its own manufactured process characteristics, primarily for performance optimization schemes like DVFS on a per-die basis, is becoming a compelling notion to the development community. That’s also being used to measure aging effects of the silicon, analyze critical timing and supply conditions on advanced-node devices, especially finFETs.”

Others agree. “There is probably even a greater need for these techniques at the advanced nodes,” said Prashant Varshney, group director of product management at Mentor, a Siemens Business. “These nodes demonstrate much larger variation in the device behaviors with the PVT conditions, forcing the designers to use more, which means if designs are implemented at the worst-case scenario, scope for the real-time PVT optimization is even higher. Designers have been struggling with the pessimism added during the design process for many past generations of process, and for each generation, when the designers feel like it is not feasible to meet design specs using the previous methods, new concepts emerge. For example, when standard on-chip variation derates were too much to handle at the finFET nodes, advanced techniques like SBOCV (stage-based OCV) and POCV came into being so they could take the edge off the added pessimism, and make the design feasible.”

Although techniques are introduced during the design process to reduce the pessimism, the variation envelop is so large that the opportunity to do a die-by-die, PVT-by-PVT optimization is even greater, Varshney said.

DVFS and AVS have been around for years, but these are not simple techniques to deploy.

“With DVFS, the biggest task is to set the modes and when certain things should happen,” White explained. “On the other hand, AVS refers to a more closed-loop approach where it understands, ‘I’ve been idle for so long, so I’m just going to go ahead and power myself down.’ The first gives more control based on modes, and the other one’s doing it by itself. In either case, they both require design techniques.”

With DVFS, the basic idea is to scale the frequency to the demand of the workload. That is mostly controlled by the software, which in turn scales the voltage to the minimum required to operate at the current frequency.

“AVS achieves much more accurate and controlled voltage scaling in a closed loop by using the real process, voltage, and temperature (PVT) information read in from the dedicated circuits on the die,” said Varshney. “With larger variation on smaller nodes, there seems to be a larger scope of AVS, as that provides optimal voltage reduction for a given frequency, thus reducing power consumption.”

Moortec’s Allen agreed. “AVS involves the reduction of power by changing the operating conditions within an ASIC in a closed loop. DVFS is a power management technique where the voltage is increased or decreased depending upon dynamic (voltage, temperature) and static (process) in-chip conditions. Both are instrumental in optimizing in-chip conditions in different ways.”
A DVFS scheme also can be used once to take process into account, or used over time to account for temperature and even aging. “It is possible, for example, to reduce power consumption to achieve a desired speed of operation. It is also possible to take process variation across a die into account, which is being done in large SoCs today,” Allen said.

When it comes to determining how to apply AVS and DVFS for optimum benefit, Synopsys’ White noted that applications with high processing power can best take advantage of the benefits of scaling techniques. “Almost any time you see an application that needs CPUs or processing units, you would definitely try to save power for those kinds of things because you don’t want that CPU operating at full bore—especially when you’re talking about mobility and mobile phones. For instance, you don’t want your camera on all the time. I know a lot of people are already complaining about how the iPhone 6’s battery can’t even last an hour on most days now. Anything that’s very compute-intensive doesn’t always need to be 100% on. That’s where these techniques are very useful in application.”

Automotive adds complexity
With the explosion of interest in automotive, the segment also presents some unique challenges where power management is concerned. This is particularly true for the AI systems in autonomous vehicles.

In automotive, one of the big challenges is modeling how variability will affect the functioning of a chip over a period of years under conditions that have never been field-tested for advanced-node designs. Variability changes with each new rev of a manufacturing process, but it also is affected by new tools, materials and packaging approaches.

Power is a concern in multiple systems within a car, as well as the entire car as a system. But there also is a lot of high-voltage technology in automotive, so the power issues there are a bit different.

“There’s a lot of processing power in automotive,” said White. “You have to realize [techniques like AVS and DVFS] can cause a functional safety issue. If you’re doing any sort of voltage scaling, you probably have to have an external monitor, like an under/over voltage monitor, for example. You have to build in safety elements to make sure that you’re not lowering the voltage such that it would shut off something you need, like something that’s running the motor. You don’t want it to decide that it’s going to adapt a voltage, and scale itself down to zero, then turn off the motor. In an ECU unit, you probably wouldn’t want to do that without monitors.”

It would be convenient if techniques like DVFS and AVS were automated within design and implementation tools today, but it’s not that simple.

Mentor’s Varshney said for DVFS, the key is to ensure design closure at all of the DVFS voltage and frequency combinations. “Some of today’s commercial tools have ways to incorporate these techniques within the design process. For example, each combination of voltage and frequency can be treated as an operating scenario for the design, and the tools can perform tuning/timing closure for all such variations simultaneously. The frequency target converts into a different clock period for a given mode of operation, and the voltage value can be annotated to the cell on an operating corner basis, as well. One key technology, delay scaling or interpolation, is required to accommodate voltage values that are different than the characterized values in the .lib, which [some] tools can handle easily by performing interpolation between the values for other operating corners.”

White pointed out that DVFS and AVS are not necessarily automated. “How we would implement DVFS is to have voltage islands that show low voltage versus high voltage, noting that only parts of the CPU may need to be lower voltage. You would specify the different power states associated with the frequency scaling in UPF, for example. Then, from the implementation perspective, you have to make sure that all the PVT corners are there.”

And Moortec’s Allen noted that AVS and DVFS would not be used concurrently. “Generally, one or the other will be used, depending on the ASIC and the application. For example, a closed-loop AVS system uses certain structures within the chip to provide the data required to adaptively track the behavior of the silicon. AVS has applications associated with in-chip variability compensation by optimizing the voltage on the go to take in chip conditions into account for operation. It also can be used to set thermal alarms and initiate fan operation. Operating at higher speed will obviously lead to a shorter lifetime, whereas operating at optimum speed will improve the device lifetime and therefore increase its reliability.”
DVFS on the other hand can be used in a number of in-chip applications, including wafer sorting based on look-up tables (LUTs). “It can also be used to check functionality by decrementing the supply in regular steps, as well as finding the lowest centre functional voltage,” Allen said. “The voltage can then be set to just the right level for utilizing optimum power and reliability of the devices.”


Sanjay Wadhwa says:

Well written article. Indeed, transistor mismatch has become a major source of variation in current generation of SoCs. Analog design is also affected greatly and it requires exhaustive implementation of analog matching techniques and good amount of silicon area to minimize the variation in the critical transistors. An article on how mismatch variation is minimized in ultra-low voltage analog circuits at very advanced nodes such as 5nm would be helpful.

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