Variation In Low-Power FinFET Designs


One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield. While variation is generally well understo... » read more

Explaining Adaptive Voltage Scaling And Dynamic Voltage Frequency Scaling


A Q&A with Moortec CTO Oliver King. What exactly do we mean by Adaptive Voltage Scaling versus Dynamic Voltage Frequency Scaling? Adaptive Voltage Scaling (AVS) involves the reduction of power by changing the operating conditions within an ASIC in a closed loop. Dynamic Voltage Frequency Scaling (DVFS), on the other hand, is a power management technique where the voltage is increased ... » read more

Mixed Messages For Mixed-Signal


There is no such thing as a purely digital design at advanced nodes today. Even designs that have no [getkc id="37" kc_name="analog"] content are likely relying on [getkc id="38" kc_name="mixed-signal"] components such as SerDes for communications, or voltage regulators for adaptive power control. But the days of purposely attempting to integrate everything including analog and RF onto a single... » read more

Closing The Loop On Power Optimization


[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more