Mixed Messages For Mixed-Signal

What does the future of analog mixed-signal design and verification look like? Can we expect to see any methodology changes?


There is no such thing as a purely digital design at advanced nodes today. Even designs that have no analog content are likely relying on mixed-signal components such as SerDes for communications, or voltage regulators for adaptive power control. But the days of purposely attempting to integrate everything including analog and RF onto a single die may be coming to an end for many segments of the industry.

At the latest nodes, transistors do not have very good operating characteristics because analog devices and scaling have had a negative impact on their performance. Scaling also has dramatically increased the difficulty of analog design. Alternatives are becoming available for designs with sufficient volume, or those which are price-insensitive, such as 2.5D assemblies.

But new markets are popping up that are not so concerned with the latest nodes, and within those markets mixed-signal users are emerging that may require different types of tooling.

Emerging nodes
There will always be users who push the limits of technology. “Integration on a single chip remains a very economical solution for many applications that ship in large volumes,” says Mladen Nizic, product management director in the Custom IC & PCB group at Cadence. “But the mix may be changing. Designs for the most advanced process nodes contain a lot of custom circuitry. This may be custom digital, some analog, and they have to be crafted in an ‘analog-ish’ way. The requirement is to have a highly integrated flow between analog and digital in physical implementation and signoff. This may even be intensifying today.”

That isn’t for everyone, however. “For the advanced nodes integration does not happen easily,” says Sathish Balasubramanian, senior product manager for mixed signal verification at Mentor, a Siemens Business. “Many companies start by buying mixed-signal IP rather than building their own. Some will buy soft IP, which has been verified for certain corners. Then they will customize that to their needs. There appears to be quite a bit of semi-customization happening. This includes changing the process, voltage, temperature (PVT) corners, looking at how much they can lower the voltage etc.”

The latest nodes are not analog-friendly. “Designing a PLL for a 7nm finFET digital design is really hard,” says Tom Ferry, vice president of product marketing for Synopsys. “The analog design is hard. The finFET was mostly designed for digital. We need to balance the process to meet both the digital and analog needs of the integrated parts.”

The latest nodes increasingly require new types of mixed-signal IP to be included, as well. “The cost of developing a chip on the latest process nodes is so high that the design must extract as much performance as possible,” said Oliver King, CTO of Moortec. “One example involves die-monitoring IP, which is analog in nature. Performance usually involves power optimization. Traditional techniques leave too much potential on the table, and so adaptive voltage scaling and dynamic frequency scaling techniques are being adopted by a much wider part of the industry than was previously the case.”

Advanced packaging may provide some relief. Instead of having to put everything onto a single die, multi-die solutions can be deployed. An added benefit is the increase in connectivity that becomes available. “You get a significant reduction in the inductance and significant reduction in capacitance just because you don’t have to spend as much die area on bonding pads,” says Drew Wingard, CTO at Sonics. “This is a game changer. To make a connection you can have something that is 2 to 5 microns square rather than a 100 microns square, and that is a big reduction in capacitance. Suddenly you can start to use full-swing CMOS signaling in an effective way, as opposed to needing a PHY. And the elimination of the transformation of the signal, from fully synchronous digital domain into something that has gone through a PHY, has a significant power advantage.”

That creates a negative side, too. “We see the need for concurrent design of the package and the chip, especially where RF is concerned,” Nizic says. “When you have a high-performance system, even if it is a single chip in the package, it has to be considered. And there is still a lot of development required in multi-chip modules, including 2.5D, 3D, interposer, etc.”

Noise is an issue for mixed-signal designs, as well. “In the past, power noise simulations were done in silos,” says Arvind Vel, senior director of applications engineering for ANSYS. “The chip designer, package designer and the board designer would have individual supply noise budgets to meet. As long as they were within their budgets, the overall operation of the chip was guaranteed. With the diminishing noise margins in advanced technology nodes, the silo-based margining quickly leads to over-design. Having a comprehensive co-simulation of the chip, package and board is mandatory in these technology nodes.”

New markets

One emerging market that is almost the polar opposite is IoT edge devices. “Edge nodes are basically a sensor that increasingly needs to do some amount of processing, plus a means to communicate,” explains Nizic. “Another characteristic of these designs is power, and that really has to be minimized. In the past we may have thought of these as simple designs, but they are quite complex mixed-signal designs. While not large SoCs, they have very specific requirements, and power is probably a dominating concern. Power Gating and minimization has to extend to analog. The tools are improving in this area to enable verification planning so that power intent can be verified across both the analog and digital domains.”

But what make the designs different are the nodes they are being produced on. “IoT is not chasing Moore’s Law and companies are not trying to be on the most advanced nodes,” adds Balasubramanian. “Many of these devices are being targeted to 28nm or above, although some are on 20nm planar, or FD-SOI. They are integrating third-party mixed-signal IP with the digital logic. The whole chip is small, and so they are doing a lot of integration.”

The source of the IP is significant. Rather than being developed in-house, most analog content is purchased from third-party companies. “Time to market tends to be small for IoT and this makes it more likely that they will buy IP,” continues Balasubramanian. “They still need mixed-signal tools to verify that the IP works standalone and when integrated in the context of the chip and in the context of the system. So while they reduce work by buying the IP, the verification needs are still there.”

This means that many of these companies do not have designers with a deep understanding of analog or RF. As Balasubramanian puts it, digital designers often consider analog and RF to be black magic. That means they have very different demands for the tools being used to assemble and verify their designs and their focus is on power and time to market.

Analog designers are becoming quite rare within the industry. It takes many years to become a skilled analog designer, and there appear to be two significant concentrations of them. One group is within the large companies that can differentiate themselves with analog content. The other group makes up the growing third-party IP providers. Unlike the market for digital IP, there are many small players in the analog IP space. They often have very specific knowledge that allows them to produce competitive IP.

Tools for mixed-signal integration

Whether the analog components were designed in house or acquired from a third-party IP company, the flows must come together at some point. “All systems have to be verified, regardless of what path you choose to do the physical implementation and signoff,” says Nizic. “Early analysis and verification of the complete system, including analog and digital and in some cases software, continues to be a challenge.”

Fig 1: Errors in mixed-signal devices. Source: Mentor

Balasubramanian is in full agreement. “The challenge is doing top-down verification across all abstractions. You start with an abstract model of the mixed-signal blocks for system-level verification and you go down to SPICE to verify within the mixed-signal block. Users want one tool that can go all the way up in abstraction and do real number modeling, which in effect turns an analog block into a digital block, and all the way down to a SPICE-level simulator. That is the spectrum in terms of accuracy and abstraction that customers are looking for.”

Even for the traditional analog designer, there are some new demands being placed on them. “Bringing analog into the verification environment requires some new capabilities in the area of verification planning,” adds Nizic. “With mixed-signal IP I need to use more advanced planning, modeling and simulation. Applications like automotive require safety and reliability, and this demands traceability and visibility into the verification process. This demands a more digital-like methodology to be applied to analog. I have to tie the specification for the analog part to the verification so that it is always traceable and you can figure out what fails and debug it easier. When a block is verified it has to be brought into an SoC environment, and that is where transparency and models are important.”

Today, we are seeing the integration of real number modeling into SystemVerilog. “This will make it similar to or better than Verilog-AMS,” continues Nizic. “Then we can bridge the AMS and SoC verification and enable digital verification engineers to take the analog models in the SV format that they are used to with a minimum penalty in speed and turn around, for SoC verification.”

This is creating a new type of designer within many systems companies. “We are seeing teams of people being trained to write efficient real-number models,” says Balasubramanian. “This is all they do. They do not necessarily have a lot of analog design expertise. They take an IP and they presume that the IP works, but the team needs to know how it will work with the top level and the system level. They develop the abstract models for that IP.”

The analog mixed-signal market has changed significantly, driven by the advancement of process technology that is considerably more digital-friendly than analog-friendly. This is causing new avenues to be explored, both at the complex SoC level and for much simpler devices targeting IoT edge nodes. Each is taking a very different path.

What they both have in common is a need for better system-level verification tools, which is something the industry is working on. “The interaction between analog and digital verification is increasing,” concludes Nizic. “Project coordination between the tools and design teams is increasing. This is driven by technology and business requirements. It is not possible to throw things over the wall anymore.”

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  • Kev

    `Today, we are seeing the integration of real number modeling into SystemVerilog. “This will make it similar to or better than Verilog-AMS,” continues Nizic`

    No it won’t. It might make it faster than SPICE, but Verilog-AMS is a behavioral modeling language that lets you write models at any level of speed/accuracy trade-off (it’s not intrinsically slow), and it understands power (V*I) which SV cannot do.

    There has been very little movement in improving AMS design/verification for over a decade because the digital guys don’t understand it and refuse to integrate it properly, and the EDA companies like to sell separate license for tools and won’t integrate them properly. At this point it would be fairly easy to take the view that digital is just a degenerate form of analog and make all the digital models fit in an analog framework to get a unified AMS verification environment, but I’ll bet none of Sysnopsys, Mentor or Cadence will do that.