Is Design Innovation Slowing?


Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

IP Challenges Ahead


The revenue from semiconductor [getkc id="43" kc_name="IP"] has risen steadily to become the largest segment of the EDA industry. Industry forecasts expect it to keep growing at a CAGR of more than 10% for the next decade. Part one of this article examined the possibility those forecasts are wrong and that large semiconductor companies are likely to start bringing IP development back in hous... » read more

Blog Review: Aug. 9


Cadence's Paul McLellan digs into a recently discovered vulnerability in the Broadcom Wi-Fi chip used in many smartphones and why it should be a wakeup call for SoC designers. Mentor's Craig Armenti considers whether work-in-process design data management is an asset or a liability. Synopsys' Thomas M. Tuerke notes that in code, as in medicine, proper hygiene is should be treated as a con... » read more

How Much Verification Is Necessary?


Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

IoT Myth Busting


The [getkc id="76" comment="Internet of Things"] (IoT) means many things to a large number of people, but one thing is clear—every discussion involving the IoT invariably includes some rather dramatic growth predictions for how many connected devices will be sold and who will be the primary beneficiaries. While that data helps spice up speeches, and typically gets people to read and quote ... » read more

The Week In Review: Design


Tools Mentor released new software for automated set-up of PCB DFT rules. The tool extracts relevant PCB design technology from the design data to determine the correct PCB technology classification, then maps the PCB classification to the constraints associated with the applicable manufacturing processes to run only the checks necessary for the design. IP Synopsys improved the convolu... » read more

Safety Plus Security: Solutions And Methodologies


By Ed Sperling & Brian Bailey As more technology makes its way into safety-critical markets—and as more of those devices are connected to the Internet—security issues are beginning to merge with safety issues. The number of attempted cyberattacks is up on every front, which has big implications for devices used in safety-related applications. There are more viruses, ransomware, an... » read more

Safety Plus Security: A New Challenge


Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Hardware/Software Tipping Point


It doesn't matter if you believe [getkc id="74" comment="Moore's Law"] has ended or is just slowing down. It is becoming very clear that design in the future will be significant different than it is today. Moore's law allowed the semiconductor industry to reuse design blocks from previous designs, and these were helped along by a new technology node—even if it was a sub-optimal solution. I... » read more

Blog Review: May 31


Mentor's Michael White predicts that 10nm will come on the scene in a big way this year with a leap to an estimated 9% foundry market share. At the recent RISC-V Workshop, Cadence's Paul McLellan considers whether fully open-source silicon is really viable. Synopsys' Robert Vamosi investigates the security risks posed by the proliferation of connected aftermarket automotive products and a... » read more

← Older posts