Week In Review: Design, Low Power

Nvidia buys Mellanox; Sonics closes; RTL synthesis; USB4 VIP; multicore RISC-V with DSP.


Nvidia will acquire Mellanox for $6.9 billion in cash, the largest deal in the chipmaker’s history. Traditionally a PC GPU company, Nvidia has made a push into high-performance computing, particularly for AI workloads. Founded in 1999, Israel-based Mellanox focuses on end-to-end Ethernet and InfiniBand interconnect solutions and services for servers and storage. According to Nvidia, Mellanox’s technologies are used in over half of the world’s fastest supercomputers and in many leading hyperscale datacenters. The companies have a history of collaboration and worked together on several recent supercomputing projects.

Sonics has ceased operations. Founded in 1996, the company developed on-chip interconnect IP as well as hardware subsystems to manage circuit idle time and minimize energy and power consumption. Industry reports say Facebook acquired the company’s assets.

Tools & IP
Synopsys released its latest RTL synthesis product, Design Compiler NXT. New optimizations include power-driven mapping and structuring techniques, concurrent clock and data (CCD) optimization, and a new approach to distributed synthesis that does not sacrifice QoR. It shares a common library and advanced placement technologies with IC Compiler II, in addition to aligned RC, net topology, and density modeling. Early adopter AMD noted it saw significant improvement in RC and timing correlation to IC Compiler II, in addition to runtime speed-up and better timing QoR.

Cadence uncorked Verification IP (VIP) for the recently announced USB4 standard. The VIP incorporates bus functional model (BFM) and integrated protocol checkers and coverage, and includes Cadence’s TripleCheck to provide users with a verification plan that is linked to the specification and a comprehensive test suite to ensure compliance with the USB4 specification.

Synopsys debuted its Subsystem Verification Solution, Verification IP (VIP), and UVM source code test suite to support the latest USB4 specification. The VIP is based on a native SystemVerilog/UVM architecture and features built-in comprehensive coverage, verification plan, extensive protocol checks, and integration with Synopsys’ protocol-aware debug tool.

Andes Technology unveiled its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors with comprehensive DSP instruction extension. Both support up to four CPU cores and operate at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support. They provide efficient cache coherence among private level-1 caches; include an optional shared level-2 cache; and support I/O coherence for bus masters without caches.

Arm, Cadence, and Xilinx teamed up on a development platform for next-generation cloud-to-edge infrastructure based on the new Arm Neoverse N1. The System Development Platform (SDP) enables asymmetrical compute acceleration via the CCIX interconnect architecture and is silicon-proven on TSMC’s 7nm FinFET process technology. It includes a Neoverse N1-based SoC with an operating frequency of up to 3GHz, full-sized caches and large amounts of memory bandwidth for hardware prototyping, software development, system validation, and performance profiling/tuning.

The first specification for Compute Express Link (CXL), a new high-speed CPU-to-Device and CPU-to-Memory interconnect designed to improve next-generation data center performance, has been published by the CXL Consortium. Built upon PCIe 5.0, CXL provides an efficient interconnect between the CPU and platform enhancements and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions. CXL maintains memory coherency between the CPU memory space and memory on attached devices, which according to the Consortium allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. The newly-formed CXL Consortium will further develop the open industry standard and is backed by Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel, and Microsoft. The specification is available to companies that join CXL.

Silicon Mobility licensed Arteris IP’s FlexNoC interconnect IP for use in its range of OLEA Field Programmable Control Unit (FPCU) products for hybrid and electric vehicle control as part of its SILant ASIL-D functional safety integrated architecture. The interconnect is used to connect IP blocks within the chip and protect the data communications between them. Silicon Mobility cited its ability to meet requirements for on-chip functional safety data protection with extremely low latencies.

Renesas adopted Synopsys’ Fusion Compiler RTL-to-GDSII implementation solution for its high-performance automotive SoCs and mission-critical MCUs. Renesas cited improved power, performance, and full-flow productivity.

Verification 3.0 Innovation Summit: Mar. 19, 1 p.m.-8 p.m., in Santa Clara, CA. A half-day seminar focused on advanced technical content around a range of topics on verification innovation, including a keynote by former Cadence CEO Joe Costello, three sessions, and a mini exhibit and reception. The event is free but registration is required.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.

Linley Spring Processor Conference 2019: April 10-11 in Santa Clara, CA. Beginning with an overview of the processor and IP market, technologies, equipment-design, and silicon trends, the event will include talks and panel discussions on a range of topics. AI chips and IoT security are both major focuses.

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