Blog Review: May 30

AI then and now; high speed memory interfaces; critical subsystems consolidation.


Cadence’s Paul McLellan listens in as Krste Asanović explains the history of AI and the birth of neural networks, the role of GPUs, and challenges for the future.

Synopsys’ Amit Tyagi examines high speed memory interfaces with a look at the basic operations of Toggle3NAND/Toggle2NAND and how they delivers higher performance at lower power consumption.

Mentor’s Mike Santarini chats with Anne Cirkel, this year’s recipient of the Marie R. Pistilli Women in EDA award, on her beginnings in the EDA industry, moving to the U.S., and what makes teams successful.

Arm’s Freddi Jeffries looks at the use cases driving smartphone design, from an explosion in mobile gaming to on-device machine learning.

Rambus’ Aharon Etengoff provides a primer on side-channel attacks and why observing electronic behavior is so damaging to cryptographic security.

VLSI Research’s Julian West takes a look at why consolidation in the critical subsystems market appears to be coming to an end and who that will benefit.

Sonics’ Greg Ehmann explains why inter-domain switch control can tame inrush currents and how to choose the proper control method.

Silicon Labs’ Kevin Smith digs into timing issues with a rule of thumb that can be used for estimating the RMS cycle-to-cycle jitter if all you have available is the RMS period jitter.

Intel’s Jakob Engblom takes a look at the value of fault injection in virtual platforms, from cache and memory ECC to timing.

Plus, check out the highlighted blogs from last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling observes that new technology is beginning to break down barriers between form and function, with huge implications.

Technology Editor Brian Bailey questions whether a vendor can differentiate itself based on the quality of its constraint solver.

Mentor’s Matthew Ballance explains how dynamic constraints can make portable stimulus test intent more flexible, modular and reusable.

Cadence’s Frank Schirrmeister finds that after 20 years, ESL concepts have been robustly adopted.

OneSpin’s Tom Anderson contends that formal verification is at the heart of finding both introduced and random errors.

Synopsys’ Eric Huang demonstrates a USB 3.2 host and device operating together at full speed.

Aldec’s Sunil Sahoo shows how to slash latency and improve performance to win over the competitionin high-frequency trading.

Arm’s Brian Fuller invites you to contribute your insights and knowledge through Arm TechCon papers and presentations.

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