How To Close Timing With An eFPGA Hosted In An SoC


eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as... » read more