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Deriving Configuration Time For eFPGAs


Part 1 of this blog post described how to configure an eFPGA, using Achronix’s Speedcore eFPGA as an example. It explained why each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up due to its nonvolatile SRAM technology to store configuration bits. This post will detail how the configuration time is derived, once again using Speedcore eFPGA as th... » read more

The Importance Of An eFPGA’s Configuration Interfaces


eFPGAs are heralded throughout the semiconductor industry for their flexibility and programmability, especially when it comes to high-performance compute applications. Let’s take a closer look at how an eFPGA is configured. Each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up because this eFPGA employs nonvolatile SRAM technology to store its co... » read more

How To Close Timing With An eFPGA Hosted In An SoC


eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as... » read more