The Importance Of An eFPGA’s Configuration Interfaces

CPU, Serial Flash, and JTAG configuration modes each have distinct advantages.


eFPGAs are heralded throughout the semiconductor industry for their flexibility and programmability, especially when it comes to high-performance compute applications. Let’s take a closer look at how an eFPGA is configured.

Each instance of the eFPGA in an ASIC or SoC design must be configured after the system powers up because this eFPGA employs nonvolatile SRAM technology to store its configuration bits. Each instance contains its own FPGA configuration unit (FCU) that initializes, configures and manages the eFPGA’s core logic array.

For example, instantiating three eFPGAs in an ASIC or SoC design will include three FCUs on the chip, each with its own set of configuration pins and configuration-mode pins to determine how the configuration pins will operate.

Figure 1: In an ASIC or SoC design, the Speedcore eFPGA’s boundary logic includes the FCU and the eFPGA’s core logic.

As figure 1 illustrates, the FCU’s configuration-mode pins feed three mode-dependent blocks marked CPU, Flash and JTAG, the three types of configuration interfaces available in the FCU. The FCU’s configuration-mode pins along with a register-based setting in the eFPGA’s JTAG controller determine how the configuration pins operate.

Configuration-mode pins alone can select between the CPU and Flash modes. The JTAG configuration mode, however, is independent of the configuration-mode pins and enabled by sending FCU commands that set the appropriate bits in the eFPGA’s JTAG TAP controller. Once JTAG mode is enabled, it overrides the settings of the configuration-mode pins until disabled, allowing the JTAG controller to take control of the eFPGA regardless of the configuration-mode settings.

Each of these three configuration modes –– CPU, Serial Flash and JTAG –– has distinct advantages.

CPU Configuration Mode
The FCU’s CPU configuration mode allows an external CPU to act as a master to control the programming operations for the eFPGA, which acts as a slave in this mode. The CPU mode operates over a 1-, 8-, 16-, 32-, or 128-bit wide parallel interface.

CPU mode is Speedcore eFPGA’s fastest possible configuration mode because it permits the eFPGA’s configuration bitstream to enter the FCU over a 128-bit bus (in its widest configuration) at the maximum supported clock rate. All eFPGA configuration modes support a 100 MHz maximum clock rate, so the maximum bitstream configuration data rate in the CPU configuration mode is a brisk 12.8 Gbits/sec.

Serial Flash Configuration Mode
The FCU’s Speedcore eFPGA’s Serial Flash configuration mode allows the FCU to load configuration bitstreams from SPI serial NOR flash memories. In this mode, the eFPGA is the master and supplies the clock to the SPI flash memory. As with the CPU configuration mode, the Serial Flash configuration mode’s maximum clock rate is 100 MHz.

However, not all serial flash devices can operate at 100 MHz. To accommodate this potential limitation, the FCU can drive the flash memory’s clock at three additional clock rates derived from the clock supplied by the ASIC/SoC to the FCU. The four available clock rates for the serial Flash memory are:

  • Divide by 1 (full speed)
  • Divide by 2
  • Divide by 4
  • Divide by 8 (default)

The clock rate is selected when generating the configuration bitstream using Achronix’s ACE design tools. Selection is configured using the “Serial Flash Clock Divider” drop-down menu in the “Bitstream Generation Implementation Options” section of the ACE GUI. Initially at power up, the FCU’s Serial Flash configuration mode operates with a divide-by-8 flash clock because it’s the safest clock rate, compatible with any flash memory device. An FCU command embedded early in the configuration bitstream can then increase the flash memory’s clock rate as set by the tools to decrease the overall configuration time while loading the configuration from the serial flash memory.

The Speedcore eFPGA’s Serial Flash mode is designed for use with 1-bit-wide flash devices. As well, it is possible to operate in a 4-bit mode that accepts one bit from each of four 1-bit-wide flash devices (as shown in the figure below). This results in faster configuration times and permits the storage of larger configuration bitstreams.

Figure 2: While Serial Flash mode is used with 1-bit-wide flash devices, it can operate in 4-bit mode that accepts one bit from each of four 1-bit-wide flash devices for faster configuration times and larger configuration bitstream storage.

JTAG Configuration Mode
The FCU’s JTAG configuration mode employs the eFPGA’s JTAG Tap controller that complies with IEEE Standard 1149.1. Because the JTAG implementation is used for bitstream programming and real-time, in-system control and observation, the JTAG TAP controller can take control of the FCU upon receipt of the appropriate data register (DR) command, regardless of the eFPGA’s configuration-mode pin settings.

When set to JTAG configuration mode using a JLOAD DR instruction, the Speedcore TAP controller accepts configuration data supplied by the JTAG port on the ASIC or SoC’s JTAG TDI data-input pin and converts it into instructions for the JTAG logic within the FCU. The JTAG logic in the FCU uses these DR instructions to assemble standard 128-bit configuration frames forwarded to the FCU state machines that load the eFPGA’s configuration memory and configure the eFPGA’s core logic.

Although the JTAG port can operate at a maximum 100 MHz clock rate like the eFPGA’s other configuration modes, the JTAG configuration mode is the slowest of the three. That’s because it is a 1-bit interface plus the substantial communications overhead bits added to the configuration bitstream to conform to JTAG instruction protocols.

When designers configure an eFPGA, they need to consider programming times as well. In part two of this two-part blog series, configuring programming times will be explored using the three eFPGA configuration modes discussed above.

For more in-depth configuration techniques, including ways to connect multiple Speedcore eFPGA cores to one CPU core on ASIC or SoC, bitstream encryption features, and CRC error checking, download the Speedcore Configuration User Guide (UG061).

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