Research Bits: Mar. 9


Low noise clock generator Researchers from Ulsan National Institute of Science and Technology (UNIST) designed a low power semiconductor circuit capable of generating high-quality clock signals with significantly reduced noise levels. The injection-locked clock multiplier (ILCM) circuit uses a simplified design based on a ring voltage-controlled oscillator (VCO). It integrates a frequency t... » read more

Robust Dynamic Voltage Droop Mitigation And Power Management


Power management is one of the keys for developing successful semiconductors products. There are virtually no applications for which power consumption is not a concern. Many creative solutions have been developed to reduce and manage power. Making these schemes work robustly in real-world conditions can be a challenge. This post considers widely used methods—voltage droop/glitch detection and... » read more

All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design


A new technical paper titled "A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems" was published by researchers at Hongik University, Seoul, South Korea. "An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digi... » read more