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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

State Of The Market For Edge Silicon
By Ed Sperling - 08 Apr, 2026 - Comments: 0

The explosion of data and the rapid ramp of AI is causing significant changes in how chips are architected. At the edge, the key metrics are power, latency, and performance, but those can vary significantly by application and by workload. Steve Roddy, chief marketing officer at Quadric, talks about the need to balance performance and efficiency with flexibility for different applications, what ... » read more

AI’s Potential And Limitations In Chip Design
By Ed Sperling - 01 Apr, 2026 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the opportunities and challenges of using AI in chip design, with Thomas Andersen, vice president for AI & Machine Learning at Synopsys; Sridhar Boinapally, senior director of analog/mixed signal tools/flow at Intel; Alex Starr, corporate fellow at AMD; Stuart Oberman, vice president for GPU hardware engineering at Nvidia; ... » read more

Challenges In Scaling Chips To 2nm And Below
By Ed Sperling - 30 Mar, 2026 - Comments: 0

Key Takeaways Scaling to 2nm and below continues due to power improvements per watt, but progress is much more challenging and costly. Solutions to problems often create other problems due to less margin for tradeoffs, often requiring larger interposers, more chiplets, and more complex packages. New levels of precision are required throughout the design-through-manufacturing flow, re... » read more

Memory For AI At The Edge
By Ed Sperling - 18 Mar, 2026 - Comments: 0

Inferencing at the edge has very different needs than training large language models or large-scale inferencing in AI data centers. Many edge devices run on a battery. They're price-sensitive, and they are constrained by the physical area of the device. As a result, the amount of memory that can be packed into these devices is also limited. Steve Woo, Rambus fellow and distinguished inventor, t... » read more

How AI Will Automate Chip Design
By Ed Sperling - 17 Mar, 2026 - Comments: 0

AI has been used in EDA for many years for the core algorithms in tools, but it's getting smarter and more optimized with the rollout of generative and agentic AI. As it evolves and improves, hardware engineers are finding ways to leverage it for more complex tasks. Ziyad Hanna, corporate vice president at Cadence, talks about five levels of autonomy in chip design that mirror those in the auto... » read more

Improving Yield Through Shared Data
By Ed Sperling - 11 Mar, 2026 - Comments: 0

Increasing complexity due to advanced packaging, multi-die assemblies, and more devices under test is having an impact on yield, which in turn slows time to market and impacts overall chip costs. What's needed is a way to share data that previously was siloed by chipmakers, fabs, and OSATs. Jayant D'Souza, technical product director at Siemens EDA, talks about the underlying drivers for sharing... » read more

Digital Twins: The Cloud’s The Limit
By Ed Sperling - 10 Mar, 2026 - Comments: 1

Key Takeaways Digital twins are gaining traction as a way of testing different options at every step of the design-through-manufacturing flow. AI can be used to glue together disparate data types in multi-physics simulations. The promise of digital twins is huge, but multiple challenges need to be solved before it can live up to its potential. Digital twin technology is draw... » read more

New Challenges In Signoff
By Ed Sperling - 03 Mar, 2026 - Comments: 0

Multi-die assemblies coupled with leading-edge process nodes make signoff increasingly challenging and scary. There are more corner cases and more data to consider, but no slack in the delivery schedule. Marc Heyberger, product engineer group director at Cadence Design Systems, talks about full-chip timing, flat versus hierarchical timing analysis, the ongoing development of full 3D-ICs, and wh... » read more

Verifying Scale-Up And Scale-Out In Data Centers
By Ed Sperling - 26 Feb, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

New Performance Requirements For Audio
By Ed Sperling - 23 Feb, 2026 - Comments: 0

Demand for higher performance in audio is rising as human-machine interactions increase on the edge. That means more processing elements, and more challenges in keeping data consistent across those processors. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the advantages of coherent designs, how that impacts security, and how DSPs are evolving ... » read more

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