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Author's Latest Posts


Why Test Costs Will Increase


The economics of test are under siege. Long seen as a necessary but rather mundane step in ensuring chip quality, or a way of testing circuitry from the inside while it is still in use, manufacturers and design teams have paid little attention to this part of the design-through-manufacturing flow. But problems have been building for some time in three separate areas, and they could have a b... » read more

Lab-To-Fab Testing


Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

The Next Big Chip Companies


Rambus’ Mike Noonen looks at why putting everything on a single die no longer works, what comes after Moore’s Law, and what the new business model looks like for chipmakers. https://youtu.be/X6Kca8Vm-wA » read more

eFPGA vs. FPGA Design Methodologies


Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. https://youtu.be/Vwo3ktQvcKc » read more

Using High-Bandwidth Memory


eSilicon’s Tim Horel talks about HBM, what engineers need to know to work with this technology, and how it integrates with ASICs at advanced nodes. https://youtu.be/0Yq2XHGF6UE » read more

EDA, IP Revenues Up Again


EDA and IP revenues were up across the board yet again, buoyed by growth across a number of new markets and an increase in new and existing companies developing chips for those markets. All told, revenue grew to $2.39 billion in Q2 of 2018, an 8.2% increase over the $2.21 billion reported in the same period in 2017, according to numbers released today by the ESD Alliance's Market Statistics ... » read more

Planning Out Verification


OneSpin Solutions’ Nicolae Tusinschi talks with Semiconductor Engineering about how to move from specification to signoff in a verification flow. https://youtu.be/2zrgaq2I1SQ » read more

Thermal Impact On Reliability At 7/5nm


Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

What Will Intel Do Next?


The writing is on the wall for big processor makers. Apple, Amazon, Facebook and Google are developing their own processors. In addition, there are more than 30 startups developing various types of AI accelerators, as well as a field of embedded FPGA vendors, a couple of discrete FPGA makers, and a slew of soft processor cores. This certainly hasn't been lost on Intel. As the world's largest... » read more

Betting Big On Discontinuity


Wally Rhines, president and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about the booming chip industry, what's driving it, how long it will last and what changes are ahead in EDA and chip architectures. What follows are excerpts of that conversation. SE: The EDA and semiconductor industries are doing well right now. What's driving that growth? Rhine... » read more

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