tag: Cadence

Blog Review: May 30
By Jesse Allen - 30 May, 2018 - Comments: 0

Cadence's Paul McLellan listens in as Krste Asanović explains the history of AI and the birth of neural networks, the role of GPUs, and challenges for the future. Synopsys' Amit Tyagi examines high speed memory interfaces with a look at the basic operations of Toggle3NAND/Toggle2NAND and how they delivers higher performance at lower power consumption. Mentor's Mike Santarini chats with A... » read more

The Week In Review: Design
By Jesse Allen - 25 May, 2018 - Comments: 0

Tools & IP Cadence and National Instruments are teaming up with the aim of improving the semiconductor development and test process. The two companies are jointly working on common transistor models to ensure consistent simulation behavior between NI AWR Microwave Office circuit design software and the Cadence Spectre simulation platform. Cadence also launched the Virtuoso RF Solution for ... » read more

Commoditizing Constraints
By Brian Bailey - 24 May, 2018 - Comments: 2

Preparing articles for Semiconductor Engineering involves talking to a lot of people and then trying to fit their statements together in a way that is logical and fair. Sometimes a subject will come up in one of these calls that is not really on topic, but is still interesting. One such incident happened this week while doing research for the Verification 3.0 article. The topic was constrain... » read more

Electronic System-Level Design: Are We There Yet?
By Frank Schirrmeister - 24 May, 2018 - Comments: 0

I am writing this while attending NI Week in Austin and am admittedly wowed by National Instruments’ open test platform. NI Week’s theme is “Developing the Future Faster.” The Tuesday keynote included guest speakers from Mazda, Honeywell, and NXP, and these were great examples of system-level design of different scopes, from cars to distributed systems to chips enabling them. Personally... » read more

Analog Migration Equals Redesign
By Ann Steffora Mutschler - 24 May, 2018 - Comments: 1

Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes. In the finFET era, those challenges have only intensified for analog circuits. Reuse, fo... » read more

Get Ready For Verification 3.0
By Brian Bailey - 24 May, 2018 - Comments: 0

Jim Hogan, managing partner of Vista Ventures, LLC, is perhaps the best-known investor in the EDA space. Recently, he has been focusing time and attention on verification startups, including cloud technology company Metrics, and Portable Stimulus pioneer Breker Verification Systems. This adds to his longer-term commitment to formal verification with OneSpin Solutions. These companies are part ... » read more

CEO Outlook On Chip Industry
By Ed Sperling - 24 May, 2018 - Comments: 1

Semiconductor Engineering sat down with Wally Rhines, president and CEO of Mentor, a Siemens Business; Simon Segars, CEO of Arm; Grant Pierce, CEO of Sonics; and Dean Drako, CEO of IC Manage. What follows are excerpts of that conversation. L-R: Dean Drako, Grant Pierce, Wally Rhines, Simon Segars. Photo: Paul Cohen/ESD Alliance SE: What are the big changes ahead, and where do you see th... » read more

Backchannel Modeling And Simulation Using Recent Enhancements To The IBIS Standard
By Cadence - 23 May, 2018 - Comments: 0

Recent enhancements to the upcoming IBIS standard now support backchannel training, enabling IBIS-AMI models to emulate this real-world SerDes behavior. AMI modelers now can incorporate backchannel algorithms into their IBIS-AMI models, automating the optimization of transmitter and receiver equalization settings in the same manner as their actual SerDes hardware devices. This saves system desi... » read more

EDA In The Cloud
By Brian Bailey - 23 May, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Blog Review: May 23
By Jesse Allen - 23 May, 2018 - Comments: 0

Cadence's Paul McLellan digs into the problems of test for 3D ICs s well as new approaches to cell-aware test, modular test and realistic IR drop at CDNLive EMEA. Mentor's Colin Walls shares four more embedded software tips, including always initializing a variable and when to use ++i instead of i++. Synopsys' Taylor Armerding points to a new way that phishing attacks could get around Mic... » read more

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