Blog Review: Mar. 6


Synopsys' Snigdha Dua traces the evolution of memory from SDRAM to DDR5 and the techniques that provide each generation's speed increase. Cadence's Paul McLellan digs into the challenges of 112Gbps SerDes, including what makes PAM4 signaling different from NRZ and what goes into equalization and modeling. Mentor's Rich Edelman provides a quick tutorial on how to set up a custom UVM report... » read more

New Design Approaches At 7/5nm


The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Week In Review: Design, Low Power


Tools & IP OneSpin Solutions debuted the Hardware Metric Calculation (HMC) App, which uses automatically extracted design information to calculate key hardware metrics to comply with functional safety standards. In particular, it focuses on automotive and autonomous driving SoCs needing to meet the highest functional safety requirements defined by the ISO 26262 standard. The HMC App calcul... » read more

Hot Technologies In Cold Weather


It is a busy week for verification and software development. DVCon in San Jose; Embedded World in Nuremberg, Germany; and Mobile World Congress (MWC) in Barcelona, Spain are all happening at the same time. I ended up covering embedded software in Germany (as I also had a paper on “Shift Left” here). At chilly minus 1° Celsius in the morning, the technologies had to be pretty hot to warm me... » read more

The Problem With Post-Silicon Debug


Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

Can Debug Be Tamed?


Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Unified Compression and LBIST in a Physically Aware Environment


Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

Blog Review: Feb. 27


Mentor's Harry Foster checks out the trends in language and library adoption for IC/ASIC designs and finds increased adoption of SystemVerilog for both design and verification while UVM remains the dominant verification methodology. Synopsys' Taylor Armerding chats with Chris Clark of Synopsys and Tim Weisenberger of SAE about the weakest points in automotive security and why it's time to mo... » read more

Partitioning Drives Architectural Considerations


Semiconductor Engineering sat down to explore partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical mar... » read more

Week In Review: Design, Low Power


Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

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