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System-Level Packaging Tradeoffs


Leading-edge applications such as artificial intelligence, machine learning, automotive, and 5G, all require high bandwidth, higher performance, lower power and lower latency. They also need to do this for the same or less money. The solution may be disaggregating the SoC onto multiple die in a package, bringing memory closer to processing elements and delivering faster turnaround time. But ... » read more

New Architectures, Much Faster Chips


The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

Moore’s Law Enters The 4th Dimension


The basic idea that more transistors are better hasn't changed in more than half a century. In fact, the overriding theme of a number of semiconductor conferences this month is that we will never have enough compute capability or storage capacity. In the past, when the number of transistors in a given area actually did double every 18 to 24 months, increasing density per square millimeter fo... » read more

Better Security, Lower Cost


For years, chipmakers have marginalized security in chips, relying instead on software solutions. Eventually that approach caught up with them, creating near panic in a scramble to plug weaknesses involving speculative execution and branch prediction, as well as the ability to read the data from chips with commercially available tools such as optical probes. There were several reasons for th... » read more

Rethinking Competitive One Upmanship Among Foundries


The winner in the foundry business used to be determined by who got to the most advanced process node first. For the most part that benchmark no longer works. Unlike in the past, when all of the foundries and IDMs competed using basically the same process, each foundry has gone its own route. This is primarily due to the divergence of end markets, and the realization that as costs increase, ... » read more

Smaller Nodes, Much Bigger Problems


João Geada, chief technologist at Ansys, sat down with Semiconductor Engineering to talk about device scaling, advanced packaging, increasing complexity and the growing role of AI. What follows are excerpts of that conversation. SE: We've been pushing along Moore's Law for roughly a half-century. What sorts of problems are you seeing now that you didn't see a couple nodes ago? Geada: The... » read more

Power Impact At The Physical Layer Causes Downstream Effects


Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Winners And Losers At The Edge


The edge is a vast collection of niches tied to narrow vertical markets, and it is likely to stay that way for years to come. This is both good and bad for semiconductor companies, depending upon where they sit in the ecosystem and their ability to adapt to a constantly shifting landscape. Some segments will see continued or new growth, including EDA, manufacturing equipment, IP, security an... » read more

New Approaches For Dealing With Thermal Problems


New thermal monitoring, simulation and analysis techniques are beginning to coalesce in chips developed at leading-edge nodes and in advanced packages in order to keep those devices running at optimal temperatures. This is particularly important in applications such as AI, automotive, data centers and 5G. Heat can kill a chip, but it also can cause more subtle effects such as premature aging... » read more

Making Silicon Photonics Chips More Reliable


Silicon photonics has the ability to dramatically improve on-die and chip-to-chip communication within a package at extremely low power, but ensuring that signal integrity remains consistent over time isn't so simple. While this technology has been used commercially for at least the past decade, it never has achieved mainstream status. That's mostly due to the fact that Moore's Law scaling h... » read more

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