Wirebonding Is Here To Stay


Few technologies in semiconductor manufacturing have stood the test of time as steadfastly as wirebonding. This process, which involves electrically connecting semiconductor devices to their packages, has been a cornerstone of the electronics industry since the beginning of the electronics industry. Like everything else in the semiconductor market, wirebonding technologies have changed over ... » read more

Wafer Scale Transfer of 2D Materials, Graphene


A new technical paper titled "Assessment of Wafer-Level Transfer Techniques of Graphene with Respect to Semiconductor Industry Requirements" was published by researchers at Infineon Technologies AG, RWTH Aachen University, Protemics, and Advantest. Abstract "Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based electronic devices typically requ... » read more

How Far Will Copper Interconnects Scale?


As leading chipmakers continue to scale finFETs — and soon nanosheet transistors — to ever-tighter pitches, the smallest metal lines eventually will become untenable using copper with its liner and barrier metals. What comes next, and when, is still to be determined. There are multiple options being explored, each with its own set of tradeoffs. Ever since IBM introduced the industry to c... » read more

Cu/SiO₂ Hybrid Bond Interconnects


Technical paper titled "Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests" from researchers at TU Dresden and others. Abstract: "The focus of this study is a detailed characterization of hybrid Cu/SiO 2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch... » read more

Investigation of integrated factors in the occurrence of copper wire bonding corrosion of semiconductor packages


Abstract "Copper wire bonding has got attracted attention over gold wire bonding due to its lower cost. However, despite many unique aspects and properties of copper wire bonding, corrosion of copper wire bonding has become a point of interest as it leads to the failure of semiconductor packages. Current and future trends and development in miniaturization and multifunction of the semico... » read more

Flat-surface-assisted and self-regulated oxidation resistance of Cu(111)


Abstract "Oxidation can deteriorate the properties of copper that are critical for its use, particularly in the semiconductor industry and electro-optics applications. This has prompted numerous studies exploring copper oxidation and possible passivation strategies. In situ observations have, for example, shown that oxidation involves stepped surfaces: Cu2O growth occurs on flat surfaces as a ... » read more

Big Changes In Tiny Interconnects


One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, th... » read more

What Is DRAM’s Future?


Memory — and DRAM in particular — has moved into the spotlight as it finds itself in the critical path to greater system performance. This isn't the first time DRAM has been the center of attention involving performance. The problem is that not everything progresses at the same rate, creating serial bottlenecks in everything from processor performance to transistor design, and even the t... » read more

New Developments Of Copper Plating Technology For Embedded Power Chip Packages Challenges


Copper plating has been extensively employed in the fabrication of embedded packaging to reach high-density, high-speed, high performance electronic products. With through holes (TH) as well as blind via aspect ratios increase, development of a reliable plating technology is very important. When the depth of through hole was over 200µm, it is difficult to fill without void by using direct curr... » read more

Keeping Up Power And Performance With Cobalt


Chip designers require simultaneous improvements in “PPAC”: power, performance and area/cost (Fig. 1). Achieving these improvements is becoming increasingly difficult as classic Moore's Law scaling slows. What's needed is a new playbook for the industry consisting of new materials, new architectures, new 3D structures within the chip, new methods to shrink feature geometries, and advanced p... » read more

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