tag: ANSYS

Blog Review: July 10
By Jesse Allen - 10 Jul, 2024 - Comments: 0

Cadence's Paul Graykowski suggests using real number modeling to streamline digital mixed-signal verification using logic simulators and hardware emulators. Siemens' John McMillan and Microsoft's Amit Kumar introduce the basics of 3D-IC, describe the flow and data management challenges, look at the evolution of TSMC 3DBlox 1.0 and 2.0, and detail a physical verification and reliability analy... » read more

Digital Twins Find Their Footing In IC Manufacturing
By Laura Peters - 09 Jul, 2024 - Comments: 0

Momentum is building for digital twins in semiconductor manufacturing, tying together the various processes and steps to improve efficiency and quality, and to enable more flexibility in the fab and assembly house. The movement toward digital twins opens up a slew of opportunities, from building and equipping new fabs faster to speeding yield ramps by reducing the number of silicon-based tes... » read more

Thermal Challenges Multiply In Automotive, Embedded Devices
By Karen Heyman - 02 Jul, 2024 - Comments: 0

Embedding chips into stacked-die assemblies is creating thermal dissipation challenges that can reduce the reliability and lifespan of these devices, a growing problem as chipmakers begin cramming chiplets into advanced packages with thinner substrates between them. In the past, nearly all of these complex designs were used in tightly controlled environments, such as a large data center, whe... » read more

Verification Tools Straining To Keep Up
By Brian Bailey - 01 Jul, 2024 - Comments: 0

Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

Chip Industry Week In Review
By The SE Staff - 28 Jun, 2024 - Comments: 0

The Design Automation Conference morphed into the Chips to Systems Conference, reflecting an industry shift from monolithic SoCs to assemblies of chiplets in various flavors of advanced packaging. The change drew a slew of students and a resurgent buzz, fueled by discussions about heterogeneous integration, reliability, and ways to leverage AI/ML to speed up design and verification processes. ... » read more

Digital Twins Gaining Traction In Complex Designs
By Ann Mutschler - 27 Jun, 2024 - Comments: 0

The integration of heterogeneous chiplets into an advanced package, coupled with the increasing digitalization of multiple industry segments, is pushing digital twins to the forefront of design. The challenge in these complex assemblies is figuring out the potential tradeoffs between different chiplets, different assembly approaches, and to be able to do it quickly enough to still hit market... » read more

Data Coherence Across Silos And Hierarchy
By Brian Bailey - 27 Jun, 2024 - Comments: 0

Shift left has become a rallying cry for the chip design industry, but unless coherent data can flow between the groups being impacted, the value may not be as great as expected. Shift left is a term that encompasses attempts to bring analysis and decision-making forward in the development process. The earlier an issue can be found, the less of a problem it ultimately becomes. But in many ca... » read more

Design Flow Challenged By 3D-IC Process, Thermal Variation
By Karen Heyman - 27 Jun, 2024 - Comments: 0

3D-ICs are proving a challenge even for designers accustomed to dealing with power and performance tradeoffs, but they are considered an inevitable migration path for leading-edge designs due to the compute demands of AI and the continual shrinking of digital logic. 3D-ICs are widely viewed as the way to continue scaling beyond the limits of planar SoCs, and a way to add more heterogeneous d... » read more

Blog Review: June 26
By Jesse Allen - 26 Jun, 2024 - Comments: 0

Cadence's Neelabh Singh examines the Gen4 link recovery mechanism in USB4 Version 2.0, an autonomous process that is initiated by a router when it encounters uncorrectable error events, and identified verification challenges. Synopsys' Gary Ruggles and Priyank Shukla highlight improvements to PCIe 7.0 that will enable secure data transfers and boost bandwidth for the next generation of AI an... » read more

Advances in 3D-IC At DAC 2024
By Marc Swinnen - 26 Jun, 2024 - Comments: 0

At the 2024 Design Automation Conference and Exhibit, Ansys, in collaboration with NVIDIA, has been showcasing its latest advances in 3D-IC multiphysics analysis, visualization, and signoff. Ansys solutions are on display for thermal integrity, power integrity, signal integrity, and mechanical integrity for multi-die (3D-IC) electronic assemblies. The DAC Exhibitor Forum sessions, sponso... » read more

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