The Week In Review: Design


Startups Two new companies unveiled this week – Metrics Technologies and Movellus. Metrics Technologies is providing a Software-as-a-Service SystemVerilog simulator and verification manager that are available as pay-per-minute. This allows companies to have fully elastic system capabilities to accommodate peak simulation demand. “Cloud technology and Software as a Service business mo... » read more

The Week In Review: Design


Security Addressing the Meltdown and Spectre speculative execution vulnerabilities has not gone smoothly. Intel's firmware update caused unexpected behavior and a higher than expected number of reboots for its Haswell and Broadwell chips, leading the company to recommend users stop patching until an updated version of the patch is available. Microsoft's attempts to fix the issue left some W... » read more

Blog Review: Jan. 24


Mentor's Rich Edelman shares some tips for debugging complex UVM testbenches containing multiple agents, multiple checkers, and new HDL. Synopsys' Prasad Subudhi K. S. explains the PCIe PIPE 4.4.1 specification and the major improvements since 4.3, including better optimization in data flow and ultra-low power operations. Cadence's Paul McLellan steps back to before the Meltdown and Spect... » read more

Blog Review: Jan. 17


Mentor's Puneet Sinha identifies the key challenges, along with cost reduction and optimization opportunities, that come with using electric powertrains in autonomous vehicles. Synopsys' Robert Vamosi examines the impact of limited cellular networks on autonomous cars, and new communications protocols that could address coverage gaps. Cadence's Paul McLellan listens in as Lucian Shifren o... » read more

Tech Talk: 7nm Process Variation


Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

Turning Down The Power


Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

Performance Improvement By System Aware Substrate Noise Analysis For Mixed-signal IC


The market wants mixed ICs that are smaller and cheaper, and even provide advanced features. To satisfy this contradiction, many mixed ICs makers are reducing their bill of materials (BOM) cost by decreasing the amount of materials in the package or on a board. But these cost-effective methods can cause significant performance degradation with intensified coupling effects due to substrate noise... » read more

Blog Review: Jan. 10


Rambus' Aharon Etengoff explains the Meltdown and Spectre CPU vulnerabilities and why they could negatively affect the semiconductor industry for decades. Cadence's Paul McLellan has an explainer on Meltdown and how it's an unintended consequence of a processor behaving as intended. Mentor's Ruben Ghulghazaryan and Jeff Wilson investigate using machine learning to predict post-deposition ... » read more

Blog Review: Jan. 3


Ansys' Steve Pytel argues that increased signaling speeds and frequencies have led to signal integrity issues that circuit simulation alone cannot handle. Cadence's Paul McLellan dives into the details of Intel's 10nm process, including three layers of self-aligned quadruple patterning, contact-over-active-gate, and cobalt for contact fill. Mentor's Ron Press and Vidya Neerkundar argue th... » read more

The Trouble With Models


Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

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