tag: ANSYS

How To Optimize Products For Performance And Sustainability
By Mehru Singh - 15 May, 2025 - Comments: 0

By Mehru Singh and Tim Ebdon Developing sustainable products is key to a company's success. From complying with regulatory requirements and meeting corporate net-zero goals to providing a superior consumer experience and reducing costs, a company’s ability to design, develop, manufacture, and source parts and components sustainably strengthens its market position. While companies have deve... » read more

Blog Review: May 14
By Jesse Allen - 14 May, 2025 - Comments: 0

Siemens’ Stephen V. Chavez finds that proper PCB high voltage spacing between conductive elements is key to reliability and understanding the principles of clearance (through-air spacing) and creepage (along-surface spacing) is critical. Cadence’s Frank Ferro checks out how the new HBM4 standard boosts bandwidth and addresses key issues in the data center, including the growing size of L... » read more

E-Powertrain EMC Design And Validation
By Ansys - 14 May, 2025 - Comments: 0

In the pursuit of zero-emission vehicles, the design of the e-powertrain and its electronic systems encounters numerous challenges. From stringent regulatory requirements to the demand for enhanced performance and efficiency, the landscape is ripe with complexities. Here, simulation emerges as a vital tool, offering a pathway to navigate these challenges with precision and innovation. What y... » read more

Security Risks Mount For Aerospace, Defense Applications
By Liz Allan - 12 May, 2025 - Comments: 1

Supply chain and hardware security vulnerabilities affect all industries, but they pose additional risks for the defense sector. Over-manufacturing and re-manufacturing allow chips from friendly nations to end up in the weapons of adversaries. And side-channel attacks such as power analysis or fault injection, as well as internet-based distributed denial of service (DDoS) attacks, provide a mea... » read more

Radiation, Temperature, Power Challenges For Chips In Space
By Liz Allan - 07 May, 2025 - Comments: 0

Mission-critical hardware used in space is not supposed to fail at all, because lives may be lost in addition to resources, availability, performance, and budgets. For space applications, failure can occur due to a range of factors, including the weather on the day of launch, human error, environmental conditions, unexpected or unknown hazards and degradation of parts to chemical factors, aging... » read more

Blog Review: May 7
By Jesse Allen - 07 May, 2025 - Comments: 0

Cadence’s Mayank Bhatnagar examines the challenge of ensuring the functional safety of disaggregated designs and how UCIe can serve as a certified way to connect individual components. Siemens’ Charlie Olson explores the causes of inter-domain leakage when a DC path is formed between two power rails and how to overcome the limitations of traditional electrical rule checking. Synopsys�... » read more

Chip Industry Week in Review
By The SE Staff - 02 May, 2025 - Comments: 0

Check out the Inside Chips podcast for our behind-the-scenes analysis of changes at Intel Foundry. Intel rolled out its updated process technology roadmap this week, along with early process design kit (PDK) for its 14A gate-all-around process technology. That node will utilize high-NA EUV, and include direct contact power delivery, the second generation of its backside power delivery techno... » read more

Blog Review: Apr. 30
By Jesse Allen - 30 Apr, 2025 - Comments: 0

Cadence’s Sree Parvathy points out how electrothermal analysis can help designers understand how temperature changes affect device behavior, such as mobility, threshold voltage, and saturation to mitigate potential failures due to thermal overstress. In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the transition towards software-defined products and why companies... » read more

Security Power Requirements Are Growing
By Adam Kovac - 28 Apr, 2025 - Comments: 0

Determining how much power to budget for security in a chip design is a complex calculation. It starts with a risk assessment of the cost of a breach and the number of possible attack vectors, and whether security is active or passive. Different forms of root of trust and cryptography have different power costs. Different systems could require tradeoffs between performance and security, whic... » read more

Chip Industry Week in Review
By The SE Staff - 25 Apr, 2025 - Comments: 0

To listen to the podcast version, click here. TSMC unveiled an unusually detailed roadmap at this week's North America Technology Symposium, including future architectures for 3D-ICs for high-performance computing and small, extremely low-power chips for AR/VR glasses, and two implementations of system-on-wafer. Fig. 1: TSMC's future packaging and stacking roadmap. Source: TSMC The ... » read more

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