category: A System Perspective

category: IoT, Security & Automotive

Stitching Together A Multi-Layer PCB PDN
By Patrick Carrier - 25 May, 2023 - Comments: 0

A printed circuit board (PCB) is much like a complicated city, with a myriad of intertwined pathways for data signals and power. To meet the electric current needs of modern, high-powered integrated circuits (ICs), the power distribution network (PDN) usually consists of wide power planes on multiple layers to provide a low-resistance path for power delivery. These planes are stitched together ... » read more

Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout
By Hossam Sarhan - 27 Apr, 2023 - Comments: 0

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted verification activities “left” to earlier stages in the design flow. Finding and eliminating selected errors earlier during design and implementation, wh... » read more

System-on-Chip Design In The Cloud: One Size Does Not Fit All
By Nebabie Kebebew - 23 Mar, 2023 - Comments: 0

At an increasing pace, companies in the semiconductor ecosystem have started seriously considering the cloud for computing and storage. Some have migrated, and others are evaluating the cloud technology choices and are sizing the business impact and benefits to make the leap. Through key adoption reports, the cloud environment is proving to be beneficial for System-on-Chip (SoC) designers by pr... » read more

Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster
By Kesmat Shahin - 23 Feb, 2023 - Comments: 0

Designers everywhere know that with the increasing complexity of integrated circuits (ICs), meeting tapeout schedules has become increasingly difficult. While there are often many reasons for missing tapeouts, one critical component is the significant amount of time needed to run the signoff layout verification cycle, which contributes to overall signoff process duration. Much of this schedule ... » read more

Importance Of Qualifying IP Revisions
By Siddharth Ravikumar - 30 Jan, 2023 - Comments: 0

Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade. An IP data library consists of many views and formats, w... » read more

Ensuring ESD Protection Verification With Industry-Standard Checks
By Mark Tawfik - 21 Dec, 2022 - Comments: 0

Electronic design automation (EDA) verification of electrostatic discharge (ESD) protection is a complex task. Different integrated circuit (IC) design companies use different ESD protection approaches, different design flows, and different verification tools. To establish a consistent and comprehensive ESD EDA verification flow, the ESD Association (ESDA) provides recommended ESD compliance ch... » read more

Mastering FOWLP And 2.5D Design Is Easier Than You Think
By Bill Acito - 22 Nov, 2022 - Comments: 0

IC packaging has come into its own, where once traditional packaging was a “necessary evil,” today’s packaging can add significant value. There is an increase in functional density and flexibility by providing a platform for heterogeneous design assembly. Where designs implemented in an SoC can become too large to yield satisfactorily and too difficult to implement on one process node, pa... » read more

Considering The Power Of The Cloud For EDA
By Michael White - 27 Oct, 2022 - Comments: 0

By Michael White, Siemens EDA, in technical collaboration with Peeyush Tugnawat, Google Cloud, and Philip Steinke, AMD At DAC 2022, Google Cloud, AMD, and Calibre Design Solutions presented an EDA in the cloud solution that enables companies to access virtually unlimited compute resources when and as needed to optimize their design and verification flows. If your company is considering addin... » read more

Debug This! How To Simplify Coverage Analysis And Closure
By Yara Essam - 10 Oct, 2022 - Comments: 0

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago — f... » read more

Why Every Design IP Needs A Complete QA Methodology
By WeiLii Tan - 22 Sep, 2022 - Comments: 0

Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables modularization and re-use of design components, so that designers can leverage already-existing components as a baseline to accelerate design schedules. Therefore, it is not surprising that the usage of... » read more

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