category: Looking Past The Horizon

category: IoT, Security & Automotive

Enhancing RTL Design Efficiency: The Power And Benefits Of Integrated Development Environments
By Eldon Nelson - 25 Jul, 2024 - Comments: 0

In today's rapidly evolving semiconductor design landscape, efficiency and productivity are integral to success. It is here that Integrated Development Environments (IDEs) are making a significant impact. These software suites are much more than programming environments where designers input text or code. They represent a comprehensive ecosystem of tools, utilities, and functionalities, all des... » read more

Enabling 2.5D/3D Multi-Die Package
By Kenneth Larsen - 27 Jun, 2024 - Comments: 1

In the rapidly evolving world of ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of IC design innovation but also an increased complexity in coordination and integration. At the forefront of this technolo... » read more

AI Accelerated Migration Of Existing Designs To New Processors
By Rob van Blommestein - 30 May, 2024 - Comments: 0

In this fast-paced digital age where speed, performance, and time-to-market are king, chip designers are under pressure to deliver high-performance computing that doesn’t compromise power efficiency. The constant demand for instantaneous data processing and sharing is pushing the boundaries of innovation in chip design. With this context, we revisit and revamp the insights from the Synopsys U... » read more

How To Get The Most Out Of Gate-All-Around Designs
By Andrew Appleby - 25 Apr, 2024 - Comments: 0

The semiconductor industry has relied on finFETs, three-dimensional field-effect transistors with thin vertical fins, for many generations of technology. However, the industry is reaching the limits of how much finFETs can be shrunk while maintaining their speed and power benefits, which are crucial for artificial intelligence (AI) and machine learning (ML) applications. The solution is the gat... » read more

Rapid Timing Constraints Signoff With Automated Constraint Management
By Rimpy Chugh - 28 Mar, 2024 - Comments: 0

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a tool must be tied closely into the logic synthesis process to make it more likely that the generated gate-level netlist will meet the desired timing. Power, performance, and area (PPA) goals can o... » read more

Navigating IoT Security
By Dana Neustadter - 29 Feb, 2024 - Comments: 0

By Dana Neustadter (Synopsys), Ruud Derwig (Synopsys), and Martin Rösner (G+D) IoT expansion requires secure and efficient connectivity between machines. Integrated SIM technology and remote SIM provisioning can make this possible. Subscriber Identity Module (SIM) cards have been around for a long time, with Giesecke+Devrient (G+D) developing and delivering the first commercial SIM car... » read more

Why Is The Power Device Market So Hot Right Now?
By Dermott Lynch - 25 Jan, 2024 - Comments: 0

Growing adoption of electric vehicles (EVs) and renewable energy sources is putting the spotlight on power semiconductor devices. These power devices have always been essential in determining the efficiency of a variety of systems, from small household electronics to equipment used in outer space. But as calls to reduce carbon emissions get louder, the market for these chips continues to flouri... » read more

Shedding More Light On Photonics For Multi-Die Systems
By Kenneth Larsen - 21 Dec, 2023 - Comments: 0

By Kenneth Larsen and Twan Korthorst Photonics harness the speed of light for fast, low-power, high-capacity data transfer. A tremendous amount of data needs to be moved swiftly across different components in a multi-die system. Considering this, exploiting the advantages of light is one way to mitigate heat dissipation and energy consumption concerns while delivering fast data transmission.... » read more

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning
By Jim Schultz - 30 Nov, 2023 - Comments: 0

What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

Ensuring The Health And Reliability Of Multi-Die Systems
By Yervant Zorian - 26 Oct, 2023 - Comments: 0

From generative AI tools that rapidly produce chatbot responses to high-performance computing (HPC) applications enabling financial forecasting and weather modeling, it’s clear we’re in a whole new realm of processing power demand. Given these compute-intensive workloads, monolithic SoCs are no longer capable to meet today’s processing needs. Engineering ingenuity, however, has answered t... » read more

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