Rapid Timing Constraints Signoff With Automated Constraint Management


Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a tool must be tied closely into the logic synthesis process to make it more likely that the generated gate-level netlist will meet the desired timing. Power, performance, and area (PPA) goals can o... » read more

Navigating IoT Security


By Dana Neustadter (Synopsys), Ruud Derwig (Synopsys), and Martin Rösner (G+D) IoT expansion requires secure and efficient connectivity between machines. Integrated SIM technology and remote SIM provisioning can make this possible. Subscriber Identity Module (SIM) cards have been around for a long time, with Giesecke+Devrient (G+D) developing and delivering the first commercial SIM car... » read more

Why Is The Power Device Market So Hot Right Now?


Growing adoption of electric vehicles (EVs) and renewable energy sources is putting the spotlight on power semiconductor devices. These power devices have always been essential in determining the efficiency of a variety of systems, from small household electronics to equipment used in outer space. But as calls to reduce carbon emissions get louder, the market for these chips continues to flouri... » read more

Shedding More Light On Photonics For Multi-Die Systems


By Kenneth Larsen and Twan Korthorst Photonics harness the speed of light for fast, low-power, high-capacity data transfer. A tremendous amount of data needs to be moved swiftly across different components in a multi-die system. Considering this, exploiting the advantages of light is one way to mitigate heat dissipation and energy consumption concerns while delivering fast data transmission.... » read more

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning


What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

Ensuring The Health And Reliability Of Multi-Die Systems


From generative AI tools that rapidly produce chatbot responses to high-performance computing (HPC) applications enabling financial forecasting and weather modeling, it’s clear we’re in a whole new realm of processing power demand. Given these compute-intensive workloads, monolithic SoCs are no longer capable to meet today’s processing needs. Engineering ingenuity, however, has answered t... » read more

Accelerating Analog Design Migration


Today’s electronic chips are commonly comprised of a mix of analog, RF, and digital components, with increasing functionalities, complexities, and numbers of transistors reaching the trillions. While the digital side of the house can take advantage of automated design implementation tools, the analog world has always been more about doing things manually and in a very “custom” way—which... » read more

High-Quality Silicon With Cloud-Based Verification


New materials, vertically stacked architectures, and angstrom-level process technologies—the complexity of today’s SoCs continues to grow to meet the needs of demanding applications such as AI, autonomous vehicles, and high-performance computing. This trend only places greater pressure on verification, already notorious for being a significant bottleneck in chip development. Design teams... » read more

New Technology Accelerates Multi-Die System Simulation


AI-powered chatbots. Robotic manufacturing equipment. Self-driving cars. Bandwidth-intensive applications like these are flourishing—and driving the move from monolithic system-on-chips (SoCs) to multi-die systems. By integrating multiple dies, or chiplets, into a single package, designers can achieve scaling of system functionality at reduced risk and with faster time to market. Multi-die... » read more

Overcoming Regression Debug Challenges With Machine Learning


Development of a modern semiconductor requires running many electronic design automation (EDA) tools many times over the course of the project. Every stage, from architectural exploration and design to final implementation and manufacturing preparation, has multiple methodology loops that must be repeated again and again. Even in such a complex development flow, functional simulation stands ... » read more

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