MISing In Signoff


Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon fai... » read more

Compute And AI In Next-Generation SSD Designs


Over the last 40 years digital storage has advanced at an amazing rate. Because it operates out of sight digital storage tends to be taken for granted, but today there is more storage capacity in the devices in our pockets than what existed in mainframe computers 30 years ago. With the rise of artificial intelligence (AI) this trend will continue and the results will be nothing less than astoun... » read more

Physical Verification In The Cloud


Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool ... » read more

Implementing Mathematical Algorithms In Hardware For Artificial Intelligence


Petabytes of data efficiently travels between edge devices and data centers for processing and computing of AI functions. Accurate and optimized hardware implementations of functions offload many operations that the processing unit would have to execute. As the mathematical algorithms used in AI-based systems evolve, and in some cases stabilize, the demand to implement them in hardware increase... » read more

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond


When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did an excellent job using BJTs, but everyone knew it was MOSFET that was leading the game i... » read more

It’s All About Staying Ahead Of The Test Challenges Curve


Since the early days when semiconductor devices contained a mere handful of gates, the manufacturing test world has been focused on how to detect the greatest number of potential defects in the shortest amount of time. This fundamental goal has not changed over the years and continues at 5nm and beyond. What has dramatically changed over the years, however, is the variety of techniques used ... » read more

Is Synthesis Still Process-Independent?


For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion. With the arrival of physical synthesis, physical effects could be taken into consideration in... » read more

“Good Enough For Government Work?” Not Anymore.


When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with the company; some of them for as many as 40 years. To get an idea of how many people I’m talking about, there was a retirement party for at least 3 or 4 people every week just in our division. You can imagine tha... » read more

First Look At USB 3.2


I’m super excited to write about and show to you the world’s first USB 3.2 demonstration. Go watch the video first and then read the rest. https://youtu.be/WPUvHeq_Sgs USB 3.2 hardware and software setup We implemented our USB 3.2 Device and Host in the HAPS-80 FPGA-Based hardware prototyping platform. The platforms use USB PHYs, which are implemented in a FinFET process node. ... » read more

Design Flows At 5nm And Beyond


It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40 nanometers was the most advanced node that I ever designed SoCs at and, although it wasn’t easy back then, it pales against the myriad of challenges facing designers today. Back then, compartmentalization of function and roles was relatively easy. We do ... » read more

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