Shift-Left Low Power Verification With UPF Information Model


By Himanshu Bhatt, Shreedhar Ramachandra and Narayanan Ganesan Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power testbenches that can monitor the UPF objects and react to the state changes of UPF objects. To meet this requirement for the user to... » read more

Where Are We On The Road To Artificial Intelligence In Chip Design?


It’s hard to find an article today that doesn’t talk about how Artificial Intelligence is going to solve every possible problem in the world. From self-driving cars, to robots running an entire hotel (in Japan), to voice assistants answering your every question, it appears that every problem can be solved with AI. As so often in life, the true answer is: it depends. It depends on the nature... » read more

Building Bridges: A New DFT Paradigm


Over the last twenty years, structural testing with scan chains has become pervasive in chip design methodology. Indeed, it’s remarkable to think that most electronic devices we interact with today (think smartphones, laptops, televisions, etc.) contain hundreds to thousands of interconnected scan chains used to verify that the semiconductors were manufactured without defects. Because the imp... » read more

Accelerate SSD Software Development And System Validation


The amount of data coming at us or that we produce ourselves in our daily lives continues to grow exponentially. It’s become the norm to stream movies and TV series from Netflix, as well as upload our own videos on YouTube. On top of this, a major shift in automotive (ADAS, autonomous driving) and surveillance are boosting the amount of data exchange that is happening every second. With th... » read more

MISing In Signoff


Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon fai... » read more

Compute And AI In Next-Generation SSD Designs


Over the last 40 years digital storage has advanced at an amazing rate. Because it operates out of sight digital storage tends to be taken for granted, but today there is more storage capacity in the devices in our pockets than what existed in mainframe computers 30 years ago. With the rise of artificial intelligence (AI) this trend will continue and the results will be nothing less than astoun... » read more

Physical Verification In The Cloud


Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud trend closely from the sidelines. We have been cautious and have not embraced Cloud as much as other industries – until now. What changed this year? What is driving design companies and EDA tool ... » read more

Implementing Mathematical Algorithms In Hardware For Artificial Intelligence


Petabytes of data efficiently travels between edge devices and data centers for processing and computing of AI functions. Accurate and optimized hardware implementations of functions offload many operations that the processing unit would have to execute. As the mathematical algorithms used in AI-based systems evolve, and in some cases stabilize, the demand to implement them in hardware increase... » read more

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond


When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did an excellent job using BJTs, but everyone knew it was MOSFET that was leading the game i... » read more

It’s All About Staying Ahead Of The Test Challenges Curve


Since the early days when semiconductor devices contained a mere handful of gates, the manufacturing test world has been focused on how to detect the greatest number of potential defects in the shortest amount of time. This fundamental goal has not changed over the years and continues at 5nm and beyond. What has dramatically changed over the years, however, is the variety of techniques used ... » read more

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