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Using IP-XACT To Solve Design And Verification Problems


As today’s SoC designs grow more complex and time-to-market (TTM) pressures rise, designers are looking for techniques to build and update designs easily. Key elements for addressing these SoC challenges include the incorporation of more commercial IP components, internal design IP reuse, and extensive automation of design and verification activities. Enhanced interoperability and reusability... » read more

3D IC: Opportunities, Challenges, And Solutions


Nearly every big city reaches a point in its evolution when it runs out of open space and starts building vertically. This enables far more apartments, offices and people per square mile, while avoiding the increased infrastructure costs of suburban sprawl. Semiconductors are evolving in much the same way. Moore’s Law is slowing, and adoption of new advanced technology nodes is slowing as wel... » read more

Four Requirements To Improve Chip Design Debug


Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs were detected and diagnosed on actual devices in the bring-up lab, where both visibility and controllability are severely limited. It is certainly true that debugging the results from pre-silicon t... » read more

Optimize Physical Verification Cost Of Ownership


As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Cell Library Verification Using Symbolic Simulation


Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models describing the cell functionality, schematic derived transistor level netlists, place and route views, physical layout views, post-layout extracted netlists as well as characterized timing and power m... » read more

Early Simulation Of Multi-Cycle Paths And False Paths


Designing with synchronous clocks avoids metastability issues on clock domain crossings, but it presents its own challenges when multi-cycle and false paths are involved. A multi-cycle path (MCP) occurs when a logical function requires more than one clock cycle to produce a final, stable result. The designer must ensure that the destination register does not clock until the result is ready. Thi... » read more

AI Testing: Pushing Beyond DFT Architectures


Every day, more applications are deploying artificial intelligence (AI) system to increase automation beyond traditional systems. The continuous growth in computing demands of AI systems require designers to develop massive, highly parallel AI processor chips. Their large sizes and types of applications have a significant impact on their design and test methodologies. With thousands of repeated... » read more

Heterogeneous Computing Model Delivers Order-Of-Magnitude Performance Breakthrough


By Srinivas Kodiyalam (NVIDIA) and Samad Parekh (Synopsys) With the ever-increasing demand for more computing performance, the HPC industry is moving towards a heterogeneous computing model, where GPUs and CPUs work together to perform general-purpose computing tasks. In this heterogeneous computing model, the GPU serves as an accelerator to the CPU, to offload the CPU and to increase comput... » read more

Requirements For Exhaustive SoC Reset Domain Crossing Checks


It is common to read that the numbers of clock domains and power domains in system-on-chip (SoC) designs are increasing, but for some reason there is less discussion about resets. There is no doubt that the number of reset domains is also rising; studies have shown that the single reset of twenty years ago has been replaced by a complex network of 40-50 domains in many chips and even 150 in som... » read more

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity


The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project stage multiplies the cost by ten. Bugs that escape verification and make their way to silicon are very expensive and time-consuming to fix. The ideal is to catch as many types of issues as possible as ... » read more

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