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The Data Center Journey, From Central Utility To Center Of The Universe


High-performance computing (HPC) has taken on many meanings over the years. The primary goal of HPC is to provide the needed computational power to run a data center – a utilitarian facility dedicated to storing, processing, and distributing data. The beginning of HPC Historically, the data being processed was the output of business operations for a given organization. Transactions, custome... » read more

ECO Should Not Stand For Extended Challenge Order


There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such task. Ideally, when the design has been placed and routed (physical implementation), final analysis of timing and other metrics is performed and an engineering change order (ECO) file is issued to t... » read more

Memory Design Shift Left To Achieve Faster Development Turnaround Time


As noted in a recent blog post, demand for more memory is a common theme for many semiconductor-driven products. Artificial intelligence (AI) and machine learning (ML) algorithms rely on fast, plentiful memory for real-time performance, and storage at all levels is key to data-intensive applications. General-purpose memory devices are giving way to customized chips for applications such as AI, ... » read more

TCAD-Based Radiation Modeling Technique For Reliable Aerospace Chips


By Ian Land and Ricardo Borges We demand a lot from the electronic components that bring our devices and systems to life. This is particularly true when it comes to semiconductors for space applications. From satellites to spacecraft, aerospace and defense equipment must tolerate the most extreme of operating conditions in order to perform their jobs safely and reliably. How do you ensure... » read more

Memory Evolution Drives Requirements For Design Technology Co-Optimization


By Ricardo Borges and Anand Thiruvengadam As new technology nodes have become available, memory has been one of the most aggressive semiconductor applications to adopt advanced process technology. The relentless demand by users of electronic devices for more memory has ensured that investments in new nodes and processes would be quickly repaid by massive sales volumes. As each new node came ... » read more

The Power Of Big Data: Or How To Make Perfect 30-Minute Brownies In Only 30 Minutes


You're scrolling online, and the picture stops you in your tracks, grabs you, captivates you. Glistening chocolate pieces are, determinedly yet slowly, oozing down a moist brownie with a crisped-to-perfection, powdered topping. It sits there, confident, flaking lazily onto a bone-white china plate. It looks delicious—mouthwatering—and, apparently, you can make it with just a 30-minute inves... » read more

Next-Generation Distributed Static Timing Analysis On The Cloud


Ever-growing chip size and complexity put pressure on every step and every electronic design automation (EDA) tool in the development flow. More decisions must be made at the architectural stage, stressing virtual prototypes and high-level models. Simulations become slower and consume more memory. Formal verification struggles to achieve full proofs. Logic synthesis and layout have a harder tim... » read more

Continuous Integration And Deployment Flows With Virtual Prototypes


Not so long ago, embedded software developers huddled side by side in chilly bring-up labs, integrating and testing their code on physical prototypes of the final systems. Beyond the inconvenience, there were two major issues with this approach. The cost of replicating prototypes across a large software team was considerable, and these systems had to be maintained and managed. It became common ... » read more

Overcoming The Growing Challenge Of Dynamic IR-Drop


IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer learns. But the challenges related to IR-drop (sometimes called voltage drop) have increased considerably in recent years, especially the dynamic IR-drop in the power/ground grid as circuits swi... » read more

Intelligent Waveform Replay For Efficient Debug


There is no doubt that design reuse is essential for today’s massive system on chip (SoC) projects. No team, no matter how large or how talented, can design billions of gates from scratch for each new chip. From the earliest days, development teams have leveraged existing gate level designs and register transfer level (RTL) code whenever possible. The emergence of the commercial intellectual ... » read more

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