Signoff Of Synthesis-Optimized Registers


How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Building Multi-Agent Systems For ASIC Flows


If one AI agent can solve a problem in a certain amount of time, can multiple agents solve it faster? The answer is yes, but only if the agents have well-defined roles and targets. This is where orchestrators fit in, and why they are so critical to agentic AI. Kexun Zhang, head of research at ChipAgents, talks about what exactly AI agents are, how they can be used to solve big problems that wou... » read more

The Evolution Of UCIe


Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Overcoming Bottlenecks In Data Movement


AI is all about data. There is more data to process, store, and move, and more tradeoffs required to do that efficiently and with enough flexibility to handle changes in future workloads. Nandan Nayampally, chief commercial officer at Baya Systems, talks about networks on chip and networks across chip, what the choke points are for data movement, and where and when data coherency makes sense. » read more

Why Proof Convergence Matters


Achieving a deterministic "yes or no" answer in semiconductor verification is becoming more challenging as chip complexity increases. There are more cores, more potential interactions, and more reliance on AI to build AI chips. Ashish Darbari, CEO of Axiomise, talks about the impact of functional interactions involving safety and security, and where to look for common patterns to prevent bugs f... » read more

How AI Will Automate Chip Design


AI has been used in EDA for many years for the core algorithms in tools, but it's getting smarter and more optimized with the rollout of generative and agentic AI. As it evolves and improves, hardware engineers are finding ways to leverage it for more complex tasks. Ziyad Hanna, corporate vice president at Cadence, talks about five levels of autonomy in chip design that mirror those in the auto... » read more

New Challenges In Signoff


Multi-die assemblies coupled with leading-edge process nodes make signoff increasingly challenging and scary. There are more corner cases and more data to consider, but no slack in the delivery schedule. Marc Heyberger, product engineer group director at Cadence Design Systems, talks about full-chip timing, flat versus hierarchical timing analysis, the ongoing development of full 3D-ICs, and wh... » read more

Software-Defined Systems


Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

Challenges In Moving Data In Chips


The number of processes running simultaneously inside of chips is growing, fueled by massive increases in data from AI and sensors everywhere. The challenge now, particularly in multi-die assemblies, is how to prioritize where signals go, how quickly they move, and when they're supposed to arrive at shared memories. Andy Nightingale, vice president of product management and marketing at Arteris... » read more

Changes In Mixed-Signal IC Verification


Analog and digital engineers traditionally have worked in very different worlds. Many analog engineers for years have opted to verify analog designs by scrutinizing waveforms, while digital engineers have treated analog blocks like black boxes. But as these two areas converge in advanced SoCs and multi-die assemblies, the demarcation line between these engineering disciplines is being erased. S... » read more

← Older posts