category: Videos

category: IoT, Security & Automotive

Application-Optimized Processors
By Ed Sperling - 29 Sep, 2023 - Comments: 0

Executing a neural network on top of an NPU requires an understanding of application requirements, such as latency and throughput, as well as the potential partitioning challenges. Sharad Chole, chief scientist and co-founder of Expedera, talks about fine-grained dependencies, why processing packets out of order can help optimize performance and power, and when to use voltage and frequency scal... » read more

Challenges In Ramping New Manufacturing Processes
By Ed Sperling - 30 Aug, 2023 - Comments: 0

Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

Speeding Up Design Closure
By Ed Sperling - 23 Aug, 2023 - Comments: 0

Increasing complexity and smaller process nodes make it far more difficult to achieve design closure for chips. There are more physical effects to model, including noise, cross-talk, and double switching effects, all of which can slow the design process. Solaiman Rahim, vice president of engineering for Synopsys’ EDA Group, talks about why it’s so important to analyze violations in design, ... » read more

Using AI To Close Coverage Gaps
By Ed Sperling - 26 Jul, 2023 - Comments: 0

Verification of complex, heterogeneous chips is becoming much more difficult and time-consuming. There are more corner cases, and devices have to last longer and behave according to spec throughout their lifetimes. This is where AI fits in. It can help identify redundancy and provide information about why a particular device or block may not be able to be fully covered, and it can do it in less... » read more

RTL Restructuring Issues
By Ed Sperling - 18 Jul, 2023 - Comments: 0

Modification of modules in RTL is the last place in chip design where changes can be made relatively easily before they reach physical design, but it’s still as complicated as the design itself — and it becomes more difficult in 3D-ICs. Jim Schultz, product marketing manager for digital design implementation at Synopsys, talks about grouping and ungrouping, re-parenting, and breaking connec... » read more

Megatrends At DAC
By Ann Mutschler - 17 Jul, 2023 - Comments: 0

Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet integration, and heterogeneous integration in an SoC and package. Frank Schirrmeister, vice president solutions and business development at Arteris IP, talks about a variety of topics that fit under the DAC umbrella... » read more

The Impact Of ML On Chip Design
By Ed Sperling - 22 May, 2023 - Comments: 0

Node scaling and rising complexity are increasing the time it takes to get chips out the door. At the same time, design teams are not getting larger. What is needed is a way to automate the creative process, and to not have to start every design from scratch. This is where reinforcement learning fits in, with its ability to centralize and store “tribal knowledge. Thomas Andersen, vice preside... » read more

Challenges In Writing SDC Constraints
By Ed Sperling - 08 May, 2023 - Comments: 0

Writing design constraints is becoming more difficult as chips become more heterogeneous, and as they are expected to function longer in the field. Timing and power can change over time, and constraints need to be adjusted to that changing context. Synopsys’ Ajay Daga, group director for R&D at Synopsys, talks about the challenges in pushing constraints down to different hierarchical portions... » read more

Multi-Die Integration
By Ed Sperling - 04 Jan, 2023 - Comments: 0

Putting multiple heterogeneous chips is the way forward for improved performance and more functionality, but it also brings a host of new challenges around partitioning, layout, and thermal. Michael Posner, senior director for die-to-die connectivity at Synopsys, talks about the advantages of 3D integration, why it’s finally going mainstream, and what’s needed in the EDA tools to make this ... » read more

Testing 2.5D And 3D-ICs
By Ed Sperling - 25 Oct, 2022 - Comments: 0

Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the ... » read more

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