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EDA In The Cloud


Hagai Arbel, CEO of Vtool, talks with Semiconductor Engineering about the benefits of moving EDA tools to the cloud, why it has been slow to take off, and what will drive this trend in the future. » read more

Next-Gen SerDes Roadmap


An explosion in data is causing a series of successive bottlenecks in the data center. Priyank Shukla, product marketing manager for high-speed SerDes IP at Synopsys, digs into the performance roadmap for moving data within server racks and between different racks, where the bottlenecks are today, and how they will be addressed in the future. Related SerDes Knowledge Center Top stories... » read more

Next-Gen Design Challenges


As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

Better Quality RTL


How do you measure the quality of RTL? Philippe Luc, director of verification at Codasip, talks about identifying bugs, improving the overall quality of the verification, what happens when different blocks are used in a design, and how to improve efficiency in the verification process. » read more

High-Speed SerDes At 7/5nm


Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

Rising Packaging Complexity


Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

Speeding Up Verification Using SystemC


Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Timing Closure At 7/5nm


Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

Banking On FPGA Prototyping


Juergen Jaeger, product management director at Cadence, explains how FPGA prototyping can improve efficiency and reduce design costs, what the development costs are for various phases of the design flow, how that changes across different markets such as automotive and 5G, and why software is now the biggest knob to turn for reducing cost and time to market. » read more

Fusing Implementation And Verification


Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

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