Tech Talk: Automotive Design

NetSpeed Systems CEO Sundari Mitra talks about how to speed up the design of automotive chips. » read more

Tech Talk: Faster Simulation

Cadence’s Adam Sherer talks about how to speed up simulation in complex multi-core designs. » read more

Tech Talk: 5/3nm Parasitics

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. » read more

Tech Talk: Verification

Frank Schirrmeister, Cadence's senior group director for verification platforms, talks about what's changing in verification with 5G, machine learning, greater connectivity, advanced packaging, and the growing need to build security into designs. » read more

Tech Talk: Pseudo SRAM

eSilicon's Kar Yee Tang explains how to improve performance at 10/7nm without affecting power and area. » read more

Tech Talk: TCAM

Dennis Dudeck, IP solutions FAE at eSilicon, talks about how to save power and area with ternary content addressable memory. » read more

Tech Talk: DO-254

Aldec's Louie De Luna explains the safety critical standard for the aerospace industry and how that parallels what's happening in automotive electronics. » read more

Tech Talk: ISO 26262

Arteris' Kurt Shuler discusses what's changing in the automotive standard and how everything is supposed to work in the future. » read more

Biz Talk: ASICs

eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Tech Talk: Timing Closure

Arteris' George Janac talks about timing closure issues in advanced chips and why this has reared its head again for the first time in a decade.   Related Stories Timing Closure Issues Resurface Adding more features and more power states is making it harder to design chips at 10nm and 7nm. » read more

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